View MC68HC805PV8_1947299.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m68hc08m68h c08m68hc08m 68hc08m68hc mc68hc 05pv8 a technical data hcmos microcontroller unit mc68hc05pv8 / d rev 1.9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc(8)05pv8/a ? rev. 1.9 technical data nondisclosure agreement required mc68hc05pv8 MC68HC805PV8 mc68hc05pv8a technical data ? rev 1.9 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. is an equal opportunity/affirmative action employer. motorola and are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2001 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data revision history nondisclosure agreement required technical data ? mc68hc(8)05pv8/a revision history contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes from rev 1.5 published on september 9th, 1999 to rev 1.6 published on may 4th, 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes from rev 1.6 published on may 4th, 2000 to rev 1.7 pub- lished on december 1st, 2000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes from rev 1.7 published on december 1st, 2000 to rev 1.8 published on february 20th, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes from rev 1.8 published on february 20th, 2001 to rev 1.9 published on september 3th, 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 introduction this section contains the revision history for the mc68hc(8)05pv8/a data book. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 revision history nondisclosure agreement required changes from rev 1.5 published on september 9th, 1999 to rev 1.6 published on may 4th, 2000 changes from rev 1.6 published on may 4th, 2000 to rev 1.7 published on december 1st, 2000 changes from rev 1.7 published on december 1st, 2000 to rev 1.8 published on february 20th, 2001 changes from rev 1.8 published on february 20th, 2001 to rev 1.9 published on september 3th, 2001 section page (in rev 1.6) description of change added pv8a functionality, initial release section page (in rev 1.7) description of change 2 33 added note 3 section page (in rev 1.8) description of change 16.15.1 185 removed pc4 input hysteresis for pv8a 16.15.1 185 added pc4 input debounce time for pv8a section page (in rev 1.9) description of change 1.5 30 added mechanical specification 1.7 33 added ordering information 16.5 176 filled in typical value for i sup12 16.5 176 added i sup4a 16.12 185 added rise time specification on vdd freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
list of sections mc68hc(8)05pv8/a ? rev. 1.9 technical data list of sections nondisclosure agreement required revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table of contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 cpu and instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . 43 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16-bit programmable timer . . . . . . . . . . . . . . . . . . . . . 123 analog to digital converter . . . . . . . . . . . . . . . . . . . . . 137 pulse width modulator . . . . . . . . . . . . . . . . . . . . . . . . . 147 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 technical data ? mc68hc(8)05pv8/a list of sections freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 list of sections nondisclosure agreement required eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 program eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 fast parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . 169 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 173 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
table of contents mc68hc(8)05pv8/a ? rev. 1.9 technical data table of contents nondisclosure agreement required section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.6 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.1 vsup, vss and pvss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.2 vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3 osc1, osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.6 pa0 ? pa7/vrefh, vrefl, an1 ? 6, in, iin, out . . . . . . . . 32 1.7.7 pb0 ? pb4/tcmp1, tcmp2, tcap1, tcap2, pwm . . . . . . 32 1.7.8 ptc0 ? ptc6/tcmp1, tcmp2, tcap1, tcap2, pwm. . . . 33 1.8 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 technical data ? mc68hc(8)05pv8/a table of contents freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 table of contents nondisclosure agreement required 2.6 program eeprom/rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.7 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 section 3. cpu and instruction set 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2.4 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.4 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 53 3.6.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
table of contents mc68hc(8)05pv8/a ? rev. 1.9 technical data table of contents nondisclosure agreement required section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.7 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 8-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 16-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9 ambient exception interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.10 high temperature interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.10.1 high voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.2 low voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.3 power driver short circuit interrupt . . . . . . . . . . . . . . . . . . 75 4.11 keyboard interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.12 port c contact sense interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 75 4.13 stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5.4 external reset (reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.6 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.7 computer operating properly reset (copr). . . . . . . . . . . . . . 82 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 table of contents nondisclosure agreement required 5.7.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.7.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.7.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.7.4 cop watchdog timer considerations . . . . . . . . . . . . . . . . 83 5.7.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.8 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9 disabled stop instruction reset . . . . . . . . . . . . . . . . . . . . . . .84 5.10 high temperature reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.11 high voltage reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.12 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.13 operation in stop and wait mode . . . . . . . . . . . . . . . . . . . .85 5.14 clock monitor reset (cmr) . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.14.1 clock monitor in stop mode . . . . . . . . . . . . . . . . . . . . . . . 86 section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1.1 ultra low power mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.5.2 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
table of contents mc68hc(8)05pv8/a ? rev. 1.9 technical data table of contents nondisclosure agreement required section 7. input/output ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3 general input/output programming . . . . . . . . . . . . . . . . . . . . . 94 7.4 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 port a keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 port a pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.3 port a voltage reference for a/d converter. . . . . . . . . . . . 96 7.4.4 port a configuration register . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.5 port a interrupt status register . . . . . . . . . . . . . . . . . . . . . 98 7.4.6 operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 port b timer channels and xor function . . . . . . . . . . . . 100 7.5.2 port b pwm channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.3 i/o configuration register. . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6 port c (high voltage port) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.6.1 port c timer channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2 port c pwm channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 port c contact sense circuitry . . . . . . . . . . . . . . . . . . . . . 103 7.6.4 port c iso9141 interface . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.5 port c low side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.6.6 port c configuration register 0 . . . . . . . . . . . . . . . . . . . . 109 7.6.7 port c configuration register 1 . . . . . . . . . . . . . . . . . . . . 113 7.6.8 port c status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.9 mftest register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 section 8. core timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3.1 core timer status & control register (ctscr) . . . . . . . .119 8.3.2 computer operating properly (cop) watchdog reset. . . 121 8.3.3 core timer counter register (ctcr). . . . . . . . . . . . . . . . 121 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 table of contents nondisclosure agreement required 8.4 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.5 core timer during stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 section 9. 16-bit programmable timer 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.2 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.2.1 output compare register 1 . . . . . . . . . . . . . . . . . . . . . .127 9.3.2.2 output compare register 2 . . . . . . . . . . . . . . . . . . . . . .128 9.3.3 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.3.1 input capture register 1 . . . . . . . . . . . . . . . . . . . . . . . . 129 9.3.3.2 input capture register 2 . . . . . . . . . . . . . . . . . . . . . . . . 130 9.3.4 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.3.5 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3.6 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.5 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 section 10. analog to digital converter 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.3 a/d principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 a/d operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5 internal and master oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.6.1 a/d status and control register (adscr) . . . . . . . . . . . . 140 10.6.2 a/d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.7 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.8 a/d during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
table of contents mc68hc(8)05pv8/a ? rev. 1.9 technical data table of contents nondisclosure agreement required 10.9 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.10 conversion accuracy definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 transfer curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 10.10.2 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.3 quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.4 offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.5 gain scale error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.6 differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.7 integral linearity error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.8 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 section 11. pulse width modulator 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.1 pwm control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.2 pwm data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.4.3 pwm period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.5 pwm during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6 pwm during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.7 pwm during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.8 frame frequency examples. . . . . . . . . . . . . . . . . . . . . . . . . . 153 section 12. voltage regulator 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3 internal power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4 5v regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.5 trimming the voltage regulator . . . . . . . . . . . . . . . . . . . . . . . 156 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 table of contents nondisclosure agreement required section 13. eeprom 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.3 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . . . 158 13.4 eeprom options register (eeopr) . . . . . . . . . . . . . . . . . . 159 13.5 eeprom read, erase and programming procedures . . .160 13.5.1 read procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.2 erase procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.3 programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.6 operation in stop and wait modes. . . . . . . . . . . . . . . . . . . 161 section 14. program eeprom 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.3 programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4 eeprom protection mechanism . . . . . . . . . . . . . . . . . . . . . . 165 14.5 options register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 section 15. fast parallel interface 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.1 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . 171 section 16. electrical specifications 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
table of contents mc68hc(8)05pv8/a ? rev. 1.9 technical data table of contents nondisclosure agreement required 16.4 program and data eeprom characteristics . . . . . . . . . . . . . 175 16.5 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.6 v dd referenced pins electrical characteristics . . . . . . . . . . . 178 16.7 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.8 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.9 power supply monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.9.1 v sup related reset and interrupts . . . . . . . . . . . . . . . . . . 183 16.10 down scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 die temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 fast peripheral interface timing. . . . . . . . . . . . . . . . . . . . . . . 188 16.15 port c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 high voltage input/output (pc0 ? 4). . . . . . . . . . . . . . . . . . 189 16.15.2 contact sense circuitry to vbattery (pc0 ? 3) and to ground (pc1 ? 4 mc68hc(8)05pv8)/(pc1-3 mc68hc05pv8a) . .189 16.15.3 iso9141 driver (pc4) mc68hc(8)05pv8 . . . . . . . . . . . .190 16.15.4 iso9141 driver (pc4) mc68hc05pv8a . . . . . . . . . . . . . 190 16.15.5 low side driver (pc5/6, pvss) . . . . . . . . . . . . . . . . . . . . 191 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 table of contents nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
list of figures mc68hc(8)05pv8/a ? rev. 1.9 technical data list of figures nondisclosure agreement required figure title page 1-1 mc68hc(8)05pv8/a block diagram . . . . . . . . . . . . . . . . . . 28 1-2 mc68hc(8)05pv8/a pin assignments . . . . . . . . . . . . . . . . 29 1-3 28-pin soic mechanical dimensions . . . . . . . . . . . . . . . . . . 30 2-1 mc68hc(8)05pv8/a memory map . . . . . . . . . . . . . . . . . . . 36 2-2 i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2-3 i/o registers $0000 ? $000f . . . . . . . . . . . . . . . . . . . . . . . . . 39 2-4 i/o registers $0010 ? $001f . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-5 i/o registers $0020 ? $002f . . . . . . . . . . . . . . . . . . . . . . . . . 41 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3-2 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3-3 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3-4 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3-5 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3-6 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .69 4-2 system control register (sysctrl) . . . . . . . . . . . . . . . . . 71 4-3 interrupt control register (intcr). . . . . . . . . . . . . . . . . . . . 73 4-4 interrupt status register (intsr) . . . . . . . . . . . . . . . . . . . .73 5-1 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 78 5-2 reset and por timing diagram . . . . . . . . . . . . . . . . . . . . 81 5-3 cop watchdog timer location register (copr) . . . . . . . . 84 5-4 interrupt status register (intsr) . . . . . . . . . . . . . . . . . . . .86 6-1 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . . 90 6-2 stop and wait flowcharts . . . . . . . . . . . . . . . . . . . . . . . . 91 7-1 port i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7-2 port a configuration register (pacfg). . . . . . . . . . . . . . . .97 7-3 port a interrupt status register (paisr) . . . . . . . . . . . . . . . 98 7-4 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 technical data ? mc68hc(8)05pv8/a list of figures freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 list of figures nondisclosure agreement required 7-5 typical application: positive vgain amplifier. . . . . . . . . . . . . 99 7-6 mapping ports to timer capture channels . . . . . . . . . . . .100 7-7 i/o configuration register (iocfg) . . . . . . . . . . . . . . . . . . 101 7-8 pc0 contact sense circuitry . . . . . . . . . . . . . . . . . . . . . . . 103 7-9 pc1 ? 3 contact sense circuitry . . . . . . . . . . . . . . . . . . . . . 104 7-10 pc4 contact sense circuitry 68hc(8)05pv8 . . . . . . . . . . 104 7-11 pc4 circuitry 68hc05pv8a. . . . . . . . . . . . . . . . . . . . . . . . 105 7-12 principal characteristic of the contact sense circuitry . . .106 7-13 interrupt status register (intsr) . . . . . . . . . . . . . . . . . . .107 7-14 principle of port c low side driver . . . . . . . . . . . . . . . . . . 108 7-15 short circuit diagnostic of port c low side driver . . . . . . 109 7-16 port c configuration register 0 (pccfg0) . . . . . . . . . . . . 109 7-17 port c special signal routing . . . . . . . . . . . . . . . . . . . . . . 112 7-18 port c configuration register 1 (pccfg1) . . . . . . . . . . . . 113 7-19 port c status register (pcstr) . . . . . . . . . . . . . . . . . . . . 114 7-20 mftest register (mftest). . . . . . . . . . . . . . . . . . . . . . . 116 8-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 118 8-2 core timer status and control register (ctscr) . . . . . . 119 8-3 core timer counter register (ctcr) . . . . . . . . . . . . . . . . 121 9-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9-2 timer control register 1 (tcr1) . . . . . . . . . . . . . . . . . . . . 131 9-3 timer control register 2 (tcr2) . . . . . . . . . . . . . . . . . . . . 132 9-4 timer status register 1 (tsr) . . . . . . . . . . . . . . . . . . . . . .134 10-1 a/d status and control register (adscr) . . . . . . . . . . . .140 10-3 a/d data register (addr). . . . . . . . . . . . . . . . . . . . . . . . . 142 10-4 electrical model of an a/d input pin. . . . . . . . . . . . . . . . . . 144 10-5 transfer curve of an ideal 8-bit a/d converter . . . . . . . . . 145 11-1 pwm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11-2 pwm waveforms (pol = 0, active low), pwmpr = $ff. . 149 11-3 pwm waveforms (pol = 1, active high), pwmpr = $cf .149 11-4 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . .150 11-5 pwm data register (pwmdat) . . . . . . . . . . . . . . . . . . . . 151 11-6 pwm period register (pwmpr) . . . . . . . . . . . . . . . . . . . . 152 12-1 mftest register (mftest). . . . . . . . . . . . . . . . . . . . . . . 156 13-1 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . 158 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
list of figures mc68hc(8)05pv8/a ? rev. 1.9 technical data list of figures nondisclosure agreement required 13-2 eeprom options register (eeopr) . . . . . . . . . . . . . . . . 159 14-1 program eeprom control register (peecr) . . . . . . . . . 164 14-2 options register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 15-1 basic fast peripheral interface timing . . . . . . . . . . . . . . . 170 15-2 system control register (syscr). . . . . . . . . . . . . . . . . . . 171 16-1 low voltage reset waveform. . . . . . . . . . . . . . . . . . . . . . . 181 16-2 vsup related reset and interrupts waveforms . . . . . . . . . 183 16-3 stop recovery timing diagram . . . . . . . . . . . . . . . . . . . . . 186 16-4 timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 list of figures nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
list of tables mc68hc(8)05pv8/a ? rev. 1.9 technical data list of tables nondisclosure agreement required table title page 1-1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . . . 52 3-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . 53 3-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . . . 55 3-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . 56 3-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4-1 reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . 67 4-2 irq sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 6-1 operating mode entry conditions . . . . . . . . . . . . . . . . . . . . . 87 7-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7-2 pwm select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7-3 timer channel 1 select . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8-1 rti rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8-2 minimum cop reset times . . . . . . . . . . . . . . . . . . . . . . . . . 121 10-2 a/d clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10-1 a/d channel assignments . . . . . . . . . . . . . . . . . . . . . . . . . .141 11-1 pwm clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 11-2 frame frequency for fosc = 4.2mhz . . . . . . . . . . . . . . . . . 153 11-3 frame frequency for fosc = 2mhz. . . . . . . . . . . . . . . . . . . 153 12-1 trimming effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 13-1 erase mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 technical data ? mc68hc(8)05pv8/a list of tables freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 list of tables nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data general description nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.7 functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.7.1 vsup, vss and pvss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.2 vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.3 osc1, osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.7.5 irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.7.6 pa0 ? pa7/vrefh, vrefl, an1 ? 6, in, iin, out . . . . . . . . 32 1.7.7 pb0 ? pb4/tcmp1, tcmp2, tcap1, tcap2, pwm . . . . . . 32 1.7.8 ptc0 ? ptc6/tcmp1, tcmp2, tcap1, tcap2, pwm. . . . 33 1.8 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 general description nondisclosure agreement required 1.2 introduction the mc68hc05pv8, MC68HC805PV8 and mc68hc05pv8a microcontrollers are members of motorola ? s 68hc05 family, designed for low-cost and single-chip systems in automotive applications. they combine an hc05 core with a shell of high-voltage peripherals. throughout this book, the term mc68hc(8)05pv8/a is used to refer to all three mcus. the rom (mc68hc05pv8) version of the mcu contains the hc05 cpu with integrated voltage regulator, ram, rom, eeprom, core timer, cop watchdog, power-on reset, 16-bit programmable timer, pwm generator, standard parallel i/o, and special i/o for the automotive voltage range, including relay driver and contact monitors. bootloader and test modes are supported. the package is 28-pin soic for the rom and development version. in the flash-like development version (MC68HC805PV8), the rom is replaced by a program eeprom. each mcu is fabricated in a low-cost double-layer poly, single-layer metal, 40v, 1.2 m cmos technology. 1.3 features features of the mc68hc(8)05pv8/a include: hc05 core 28 pin soic package program eeprom or rom ? MC68HC805PV8: 7936 bytes of program eeprom + 240 bytes of monitor rom + 16 bytes user vectors ? mc68hc05pv8: 7936 bytes of rom + 240 bytes of monitor rom + 16 bytes user vectors 192 bytes of ram including stack 128 bytes of data eeprom freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
general description features mc68hc(8)05pv8/a ? rev. 1.9 technical data general description nondisclosure agreement required on-chip 5v ( 5%) voltage regulator including power-on reset, with 20ma supply for external devices. vsup range is 6v to 16v. limited operation above and below that range. breakdown voltage above 40v. on-chip oscillator with external resonator. internal bus frequency in run and wait mode is f osc 2. multipurpose core timer, real time interrupt (rti), (window) cop watchdog timer 16-bit timer with two input captures and two output compares 1 channel high-speed pwm with adjustable frame frequency 8 bit 6 channel a/d converter port a: 8 channel 5v i/o, with pull-ups, shared with a/d converter port b: 5 channel 5v i/o shared with timer and pwm port c: 7 channel 40v i/o ? 5 channel 10ma contact monitor, 1 for a switch to ground, 1 for a switch to battery and 3 of universal type. contact monitoring requires a 1k ? external resistor. contact monitor pins may alternatively be configured as high-voltage i/o relative to vsup. pins are shared with timer and pwm. ? 2 channel 2 ? ls relay driver. the pins are shared with the pwm. break-down voltage of high-voltage pins is greater than 40v. high-voltage interrupt/reset (hvi/hvr) and low-voltage reset (lvr). ? 40 c to 125 c junction temperature. operational amplifier, connected to pa4 ? 6 keyboard wake-up interrupt on port a and pc4 ? 0 iso9141 compatible transceiver on port c4 ultra low power mode on 68hc05pv8a freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 general description nondisclosure agreement required figure 1-1 mc68hc(8)05pv8/a block diagram 0 000000011 cpu control arithmetic/logic unit accumulator index register stack pointer program counter m68hc05 mcu reset condition code register 111hi ncz ddr a port a pa7/vrefh pa6/an6/in pa5/an5/iin pa4/an4/out pa3/an3 pa2/an2 pa1/an1 pa0/vrefl core timer, internal oscillator divide by 2 16-bit irq osc1 osc2 user ram ? 192bytes reset ddrb port b pb4/pwm pb3/tcmp2 pb2/tcap2 pb1/tcmp1 pb0/tcap1 ddr c port c eeprom ? 128bytes pc6/pwm pc5/pwm/tcmp1 pc4/pwm/tcmp1/ pc3/tcmp2 pc2/tcap2 pc1/tcmp1 pc0/tcap1/tcmp1/ timer cop cpu clock monitor rom ? 240 bytes 8-bit a/d converter program eeprom/user rom ? 8k user vectors ?16 bytes pwm pcfrc iocnf pvss on-chip voltage regulator vsup low voltage reset vss vdd pwm tcap1 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
general description mask options mc68hc(8)05pv8/a ? rev. 1.9 technical data general description nondisclosure agreement required 1.4 mask options there are five mask options on the mc68hc(8)05pv8/a: stop instruction (enable/disable) cop watchdog timer (enable/disable) clock monitor (enable/disable) high temperature reset (enable/disable) high voltage reset (enable/disable) 1.5 pin assignments figure 1-2 shows the 28-pin soic pin assignments. figure 1-2 mc68hc(8)05pv8/a pin assignments 1 pa0/vrefl pa1/an1 pa2/an2 pa3/an3 pa5/an5/iin pa6/an6/in pa7/vrefh vdd vsup pc0/tcap1/tcmp1/pwm pc1/tcmp1 2 3 4 5 6 7 8 9 10 11 12 13 14 pa4/an4/out pc2/tcap2 pc3/tcmp2 28 pb0/tcap1 pb1/tcmp1 pb2/tcap2 pb4/pwm reset osc2 osc1 vss pc6/pwm pvss 27 26 25 24 23 22 21 20 19 18 17 16 15 pb3/tcmp2 pc5/tcmp1/pwm pc4/tcmp1/pwm/tcap1 irq freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 general description nondisclosure agreement required 1.6 mechanical specifications figure 1-3 28-pin soic mechanical dimensions g d 28 pl c k ? t ? seating plane m f j 0.25 m b m 0.25 m b s a s t 14 pl r x 45 1 dim. min. max. notes dim. min. max. a 17.80 18.05 1. dimensions ? a ? and ? b ? are datums and ? t ? is a datum surface. 2. dimensioning and tolerancing per ansi y14.5m, 1982. 3. all dimensions in mm. 4. dimensions ? a ? and ? b ? do not include mould protrusion. 5. maximum mould protrusion is 0.15 mm per side. j 0.229 0.317 b 7.40 7.60 k 0.127 0.292 c 2.35 2.65 m 0 8 d 0.35 0.49 p 10.05 10.55 f 0.41 0.90 r 0.25 0.75 g1.27 bsc ??? case 751f-03 ? a ? ? b ? p freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
general description functional pin descriptions mc68hc(8)05pv8/a ? rev. 1.9 technical data general description nondisclosure agreement required 1.7 functional pin descriptions the following paragraphs give a description of the general function for each pin. 1.7.1 vsup, vss and pvss the microcontroller is operated from a single power supply. vsup is connected to the positive supply, vss to ground. the on-chip voltage regulator uses vsup to derive the vdd supply for the mcu and external components. pvss is a separate ground for the relay drivers. 1.7.2 vdd this pin is driven by the on-chip voltage regulator. it can be used to provide a regulated voltage to external devices. a capacitor must be attached to this pin in order to stabilize the regulator. 1.7.3 osc1, osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. a crystal connected across these pins or an external signal connected to osc1 provides the oscillator clock. the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . 1.7.4 reset this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains an internal schmitt trigger to improve its noise immunity as an input. the reset pin has an internal pull-down device that pulls the reset pin low when there is an internal cop watchdog reset, power-on reset (por), illegal address reset, internal high voltage or an internal low voltage reset. refer to section 5. resets . freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 general description nondisclosure agreement required 1.7.5 irq the interrupt triggering sensitivity of this pin can be programmed as rising/falling edge sensitive or high/low level sensitive.the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 4. interrupts for more details on the interrupts. 1.7.6 pa0 ? pa7/vrefh, vrefl, an1 ? 6, in, iin, out these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as inputs during power-on or reset. the eight i/o lines are shared with the a/d converter function (see section 10. analog to digital converter ). the internal operational amplifier is connected to pa4/out (output), pa5/iin (inverting input) and pa6/in (input) (see 7.4.6 operational amplifier ). see section 7. input/output ports for more details on the i/o ports. 1.7.7 pb0 ? pb4/tcmp1, tcmp2, tcap1, tcap2, pwm these five i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as inputs during power-on or reset. the port pins pb0 ? pb3 are shared with the 16-bit timer (tcap1 ? 2, tcmp1 ? 2). see section 9. 16-bit programmable timer for more details on the operation of the 16-bit timer. pin pb4 is shared with the pwm system (see section 11. pulse width modulator ). see section 7. input/output ports for more details on the i/o ports. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
general description ordering information mc68hc(8)05pv8/a ? rev. 1.9 technical data general description nondisclosure agreement required 1.7.8 ptc0 ? ptc6/tcmp1, tcmp2, tcap1, tcap2, pwm these seven high voltage i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as inputs during power-on or reset. the port pins pc0 ? pc5 are shared with the 16-bit timer (tcap1 ? 2, tcmp1 ? 2). see section 9. 16-bit programmable timer for more details on the operation of the 16-bit timer. pins pc0, pc4 ? 6 are shared with the pwm system. pc5 ? 6 are intended to drive relays. see section 7. input/output ports for more details on the i/o ports. 1.8 ordering information table 1-1 ordering information device package type temperature range (junction) order number (1) 1. the y in the device order number indicates that this is the junction temperature of the de- vice, not the ambient temperature. mc68hc05pv8 28-pin soic ? 40 c to +125 c mc68hc05pv8ydw MC68HC805PV8 MC68HC805PV8ydw mc68hc05pv8a mc68hc05pv8aydw freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 general description nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data memory nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6 program eeprom/rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.7 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 memory nondisclosure agreement required 2.2 introduction the mc68hc(8)05pv8/a has a 16k byte memory map consisting of registers (for i/o, control and status), user ram, user rom (or program eeprom), eeprom, monitor rom, and reset and interrupt vectors as shown in figure 2-1 . $0000 i/o registers 32 bytes $001f $0020 i/o registers 16 bytes $002f $0030 externally mapped 4-bit i/o, if enabled $003f $0040 user ram 192 bytes stack ram 64 bytes $00c0 $00ff $00ff $0100 unused 128 bytes $017f $0180 eeprom 128 bytes $01ff $0200 unused 7680 bytes $1fff $2000 mask option register ? 1 byte $2001 program eeprom/user rom 7935 bytes $3eff $3f00 monitor rom 240 bytes $3fef $3ff0 user vectors 16 bytes $3fff figure 2-1 mc68hc(8)05pv8/a memory map freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
memory registers mc68hc(8)05pv8/a ? rev. 1.9 technical data memory nondisclosure agreement required 2.3 registers the i/o and control registers reside in locations $0000 ? $002f. the overall organization of these registers is shown in figure 2-2 . the bit assignments for each register are shown in figure 2-3 , figure 2-4 and figure 2-4 . addr register name $0000 port a data register $0001 port b data register $0002 port c data register $0003 unused $0004 port a data direction register $0005 port b data direction register $0006 port c data direction register $0007 unused $0008 core timer control/status (ctcsr) $0009 core timer counter (ctcr) $000a system control register $000b unused $000c eeprom programming register $000d program eeprom programming register (1) $000e a/d data $000f a/d status/control $0010 timer capture 1 high $0011 timer capture 1 low $0012 timer compare 1 high $0013 timer compare 1 low $0014 timer capture 2 high $0015 timer capture 2 low $0016 timer compare 2 high $0017 timer compare 2 low $0018 timer counter high $0019 timer counter low $001a timer alternate counter high figure 2-2 i/o register summary freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 memory nondisclosure agreement required $001b timer alternate counter low $001c timer control 1 $001d timer control 2 $001e timer status $001f test $0020 port a configuration register $0021 i/o configuration register $0022 port c configuration register 0 $0023 unused $0024 port a interrupt status $0025 unused $0026 port c configuration register 1 $0027 port c status register $0028 interrupt control register $0029 interrupt status register $002a reset status register $002b unused $002c pwm period $002d pwm control $002e pwm data $002f mftest 1. implemented in MC68HC805PV8 only; unused in mc68hc05pv8 addr register name figure 2-2 i/o register summary freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
memory registers mc68hc(8)05pv8/a ? rev. 1.9 technical data memory nondisclosure agreement required note: * wcop bit is write once addrregisterr/wbit 7654321bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 w $0001 port b data r 0 0 tcap1 pb4 pb3 pb2 pb1 pb0 w $0002 port c data r0 pc6 pc5 pc4 pc3 pc2 pc1 pc0 w $0003 unused r w $0004 port a data direction r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w $0005 port b data direction r000 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w $0006 port c data direction r000 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w $0007 unused r w $0008 ctscr rtofrtif tofe rtie 00 rt1 rt0 w rtof rtif $0009 ctcr r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $000a system control r por intp intn inte wcop * wcp fpie fpiclk w $000b unused r w $000c eeprog r000 eeosc eer1 eer0 eelat eepgm w $000d program eeprom control r rcon bulk eepera eeplat eeppgm w $000e a/d data r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $000f a/d status/control rcoco adrc adon adtest ch3 ch2 ch1 ch0 w figure 2-3 i/o registers $0000 ? $000f freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 memory nondisclosure agreement required addrregisterr/wbit 7654321bit 0 $0010 timer input capture1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0011 timer input capture1 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0012 timer output compare1 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0013 timer output compare1 low r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w $0014 timer input capture2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0015 timer input capture2 low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $0016 timer output compare2 high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0017 timer output compare2 low r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w $0018 timer counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $0019 timer counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $001a timer alternate counter high r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w $001b timer alternate counter low r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w $001c timer control1 r ici1e ici2e oci1e toie oci2e toff w $001d timer control2 r iedge1 iedge2 clk21 0 olvl1 clk12 0 olvl2 wfolv1folv2 $001e timer status r ic1f ic2f oc1f tof oc2f si1 si2 0 w $001f test r00000000 w ???????? figure 2-4 i/o registers $0010 ? $001f freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
memory registers mc68hc(8)05pv8/a ? rev. 1.9 technical data memory nondisclosure agreement required addrregisterr/wbit 7654321bit 0 $0020 port a configuration r vrhen puhen edgeh pahie pulen edgel palie vrlen w $0021 i/o configuration r txor opamp 0 pb4pw pb3oc pb2ic pb1oc pb0ic w $0022 port c configuration 0 r isom* pc6pw pwms1 pwms0 pc3oc ts2 ts1 ts0 w $0023 unused r w $0024 port a interrupt status r paif7 paif6 paif5 paif4 paif3 paif2 paif1 paif0 w $0025 unused r w $0026 port c configuration 1 r csie scie6 scie5 pc4cs pc3cs pc2cs pc1cs pc0cs w $0027 port c status r csif scif6 scif5 csd4 csd3 csd2 csd1 csd0 w $0028 interrupt control register r ulpm 0000 htie hvie lvie w $0029 interrupt status register r rcon pc4cl 0 0 0 htif hvif lvif w $002a reset status register r pinr stopr copr ilinr cmr htr hvr lvr w $002b unused r w $002c pwm period r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w $002d pwm control r pwmon pol 0 cycle pra3 pra2 pra1 pra0 w $002e pwm data r bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 w $002f mftest r hvtoff 00 vscal lsoff vt2 vt1 vt0 w ?? figure 2-5 i/o registers $0020 ? $002f note:isom bit is without function on 68hc05pv8a note:ulpm bit is only available on 68hc05pv8a note:pc4cl is reversed on 68hc05pv8a k20r freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 memory nondisclosure agreement required 2.4 ram the user ram consists of 192 bytes ranging from $0040 to $00ff. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram in the range $00ff to $00c0. the stack is located in the ram address space. data written to addresses within the stack address range could be overwritten during stack activity. 2.5 monitor rom the monitor rom ranges from $3f00 to $3fef. the vectors for the bootloader are located from $3fe0 to $3fef. 2.6 program eeprom/rom the program eeprom holds 7952 bytes in total. the mask option register is located at address $2000. the 7935 bytes of the program eeprom are located from $2001 to $3eff, plus 16 bytes of user vectors from $3ff0 to $3fff. the user programs the eeprom on a 4 byte erase basis by manipulating the programming register located at address $000d. refer to section 14. program eeprom for details. this eeprom is replaced by an 8k rom in the mc68hc05pv8, ranging from $2000 to $3eff and $3ff0 to $3fff. mask options are controlled by the contents of location $2000. refer to section 14. program eeprom for coding details. 2.7 eeprom the 128 bytes of eeprom are located from $0180 to $01ff. the user programs the eeprom on a single-byte basis by manipulating the programming register, located at address $000c. refer to section 13. eeprom for programming details. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 3. cpu and instruction set 3.1 contents 3.2 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.3 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.4 instruction set overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.5.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.5.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.5.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.6 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.6.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 52 3.6.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 53 3.6.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.6.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . 56 3.6.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.2 cpu registers figure 3-1 shows the five cpu registers. cpu registers are not part of the memory map. 3.2.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations. figure 3-1 programming model accumulator (a) a index register (x) x sp 11 00 00 0 00 0 pcl pch zc in 1h 11 0 4 75 condition code register (ccr) program counter (pc) stack pointer (sp) 0 7 8 15 15 5 7 7 0 0 0 half-carry flag interrupt mask negative flag zero flag carry/borrow flag 10 6 bit 7654321bit 0 reset: unaffected by reset figure 3-2 accumulator freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set cpu registers mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required 3.2.2 index register in the indexed addressing modes, the cpu uses the byte in the index register to determine the conditional address of the operand. the 8-bit index register can also serve as a temporary data storage location. 3.2.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset or after the reset stack pointer (rsp) instruction, the stack pointer is preset to $00ff. the address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. the ten most significant bits of the stack pointer are permanently fixed at 000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations. an interrupt uses five locations. bit 7654321bit 0 reset: unaffected by reset figure 3-3 index register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 0000000011 reset0000000011111111 figure 3-4 stack pointer freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.2.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. the two most significant bits of the program counter are ignored internally. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.2.5 condition code register the condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. the following paragraphs describe the functions of the condition code register. half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 ?? reset ?? loaded with vector from $3ffe and $3fff figure 3-5 program counter bit 7654321bit 0 111hincz reset111u1uuu figure 3-6 condition code register freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set arithmetic/logic unit (alu) mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required interrupt mask setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is logic zero, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 3.3 arithmetic/logic unit (alu) the alu performs the arithmetic and logical operations defined by the instruction set. the binary arithmetic circuits decode instructions and set up the alu for the selected operation. most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. multiplication is not performed as a discrete operation but as a chain of addition and shift freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required operations within the alu. the multiply instruction (mul) requires 11 internal clock cycles to complete this chain of operations. 3.4 instruction set overview the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 3.5 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 3.5.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set addressing modes mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required increment accumulator (inca). inherent instructions require no operand address and are one byte long. 3.5.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 3.5.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 3.5.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 3.5.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000 ? $00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.5.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000 ? $01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 3.5.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 3.5.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two ? s complement byte that gives a branching range of ? 128 to +127 bytes from the address of the next location after the branch instruction. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction types mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 3.6 instruction types the mcu instructions fall into the following five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.6.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 3-1 register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction types mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required 3.6.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. table 3-2 read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one ? s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two ? s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.6.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ? 128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction types mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required table 3-3 jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.6.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 3-4 bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction types mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required 3.6.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 3-5 control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required 3.7 instruction set summary table 3-6 instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? ? ? ? ? ? ? ? ? imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? ? ? ? ? ?? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ?? ? ? ? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ?? ? ? ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ?? ? ? ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 c b0 b7 0 b0 b7 c freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction set summary mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ?? ? ? ? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? ? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? ? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0inh98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 3-6 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 01 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ?? ? ? ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one ? s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? ? ? ? ? 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ?? ? ?? ? ? ? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? ? ? ? ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ?? ? ? ? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? ? ? ? ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 3-6 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction set summary mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ?? ? ? ? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ?? ? ? ? ? ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ?? ? ? ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ?? 0 ?? dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0inh42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two ? s complement) m ? (m) = $00 ? (m) a ? (a) = $00 ? (a) x ? (x) = $00 ? (x) m ? (m) = $00 ? (m) m ? (m) = $00 ? (m) ?? ? ? ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ?? ? ? ? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ?? ? ? ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 3-6 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ?? ? ? ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ? ? ???? inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ?? ? ?? ? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1inh99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ?? ? ? ? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin ? 0 ??? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ?? ? ? ? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ?? ??? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 10 tax transfer accumulator to index register x (a) ????? inh 97 2 table 3-6 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
cpu and instruction set instruction set summary mc68hc(8)05pv8/a ? rev. 1.9 technical data cpu and instruction set nondisclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ?? ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 ? ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flagpc program counter ccrcondition code registerpch program counter high byte dddirect address of operandpcl program counter low byte dd rrdirect address of operand and relative offset of branch instructionrel relative addressing mode dirdirect addressing mode rel relative program counter offset byte ee ffhigh and low bytes of offset in indexed, 16-bit offset addressingrr relative program counter offset byte extextended addressing modesp stack pointer ff offset byte in indexed, 8-bit offset addressingx index register h half-carry flagz zero flag hh llhigh and low bytes of operand address in extended addressing# immediate value i interrupt mask logical and ii immediate operand byte logical or immimmediate addressing mode logical exclusive or inhinherent addressing mode( ) contents of ixindexed, no offset addressing mode ? ( ) negation (two ? s complement) ix1indexed, 8-bit offset addressing mode loaded with ix2indexed, 16-bit offset addressing mode? if mmemory location: concatenated with n negative flag ? set or cleared n any bit ? not affected table 3-6 instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data instruction set summary technical data mc68hc(8)05pv8/a ? rev. 1.9 cpu and instruction set nondisclosure agreement required table 3-7 opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 01234567 89abc def 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 tax 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherentrel = relative imm = immediateix = indexed, no offset dir = directix1 = indexed, 8-bit offset ext = extendedix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.7 external interrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.8 8-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.8.1 16-bit timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.9 ambient exception interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.10 high temperature interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.10.1 high voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.2 low voltage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.10.3 power driver short circuit interrupt . . . . . . . . . . . . . . . . . . 75 4.11 keyboard interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.12 port c contact sense interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 75 4.13 stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required 4.2 introduction the mcu can be interrupted in different ways: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt (irq) 3. external asynchronous interrupt on port a 4. external asynchronous interrupt on port c 5. internal 8-bit timer interrupt (ctimer) 6. internal 16-bit timer1 interrupt (timer) 7. low voltage interrupt 8. port c5 & c6 short circuit interrupt 9. high voltage interrupt 10. high temperature interrupt 4.3 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding interrupt enable bit is set, then the processor proceeds with interrupt processing. otherwise, the next instruction is fetched and executed. if an interrupt occurs, the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and finally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 is serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
interrupts cpu interrupt processing mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required when an interrupt is to be processed, the cpu fetches the address of the appropriate interrupt software service routine from the vector table at locations $3ff0 through $3fff as defined in table 4-1 . table 4-1 reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on logic none none 1 $3ffe ? $3fff reset pin cop watchdog low voltage high voltage mask options high temperature clock monitor illegal stop inst. illegal address none software interrupt (swi) user code none none same priority as instruction $3ffc ? $3ffd external interrupt irq pin inte bit i-bit 2 $3ffa ? $3ffb core timer interrupts rtif rtie bit i-bit 3 $3ff8 ? $3ff9 tof tofe bit 16-bit timer interrupts icf bits icie bits i-bit 4 $3ff6 ? $3ff7 ocf bits ocie bits tof bit toie bit freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required the m68hc05 cpu does not support interruptible instructions, therefore, the maximum latency to the first instruction of the interrupt service routine must include the longest instruction execution time plus stacking overhead. latency = (longest instruction execution time + 10) x t cyc an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. voltage, temperature and port c short circuit interrupts hti bit htim bit i-bit 5 $3ff4 ? $3ff5 hvi bit hvim bit lvi bit lvim bit scif6 scie6 scif5 scie5 port a high nibble interrupt port a4 ? 7pahie bit i-bit 6 $3ff2 ? $3ff3 port a low nibble interrupt port a0 ? 3 palie bit port c contact sense/hv inputs csif csie i-bit 7 $3ff0 ? $3ff1 table 4-1 reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
interrupts cpu interrupt processing mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required figure 4-1 interrupt processing flowchart y y n from reset i-bit in ccr set? clear irq request latch execute instruction restore registers from stack: ccr,a,x,pc stack pc,x,a,ccr irq? y n internal 8 bit core timer interrupt? y n internal 16 bit timer interrupt? y n high temp low/high volt, sc interrupt? y n port a wired or interrupt? y n port c0 ? 4 contact sense interrupt? fetch next instruction y swi instruction ? y n rti instruction ? n set i-bit in cc register load pc from: swi: $3ffc ? $3ffd irq: $3ffa ? $3ffb core timer: $3ff8 ? $3ff9 16-bit timer: $3ff6 ? $3ff7 t, v, sc: $3ff4 ? $3ff5 pta: $3ff2 ? $3ff3 contact sense: $3ff0 ? $3ff1 n freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required 4.4 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or internally generated rst signal causes the program to vector to its starting address which is specified by the contents of memory locations $3ffe and $3fff. the i-bit in the condition code register is also set. the mcu is configured to a known state during this type of reset as described in section 5. resets . 4.5 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), the swi instruction executes after interrupts which were pending before the swi was fetched, or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $3ffc and $3ffd. 4.6 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware interrupts which are explained in the following sections. 4.7 external interrupt (irq) if the interrupt mask bit (i-bit) of the ccr has been cleared and the interrupt enable bit is set (inte bit) and the signal of the external interrupt pin (irq ) satisfies the condition selected by the option control bits (intp and intn), then the external interrupt is recognized. inte, intp and intn are all bits contained in the system control register located at $000a. when the interrupt is recognized, the current state of freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
interrupts external interrupt (irq) mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required the cpu is pushed onto the stack and the i-bit is set. this masks further interrupts until the present one is serviced. the interrupt service routine address is specified by the contents of memory locations $3ffa and $3ffb. intp, intn ? external interrupt sensitivity options these two bits allow the user to select which edge of the irq pin is sensitive as shown in table 4-1 . both bits can be written only while the i-bit is set, and are cleared by power-on or external reset. therefore the device is initialized with negative edge and low level sensitivity. inte ? external interrupt enable 1 = external interrupt function (irq ) enabled. 0 = external interrupt function (irq ) disabled. the inte bit can be written to only while the i-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. $000a bit 7 654321bit 0 read: por intp intn inte wcop wcp fpie fpiclk write: reset:na0000000 figure 4-2 system control register (sysctrl) table 4-2 irq sensitivity intp intn irq sensitivity 00 negative edge and low level sensitive 0 1 negative edge only 1 0 positive edge only 11 positive and negative edge sensitive freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required table 4-1 describes the various triggering options available for the irq pin, however it is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to change the external interrupt options while the i-bit is set. any attempt to change the external interrupt option while the i-bit is clear will be unsuccessful. if an external interrupt is pending, it will automatically be cleared when selecting a different interrupt option. note: if the external interrupt function is disabled by the inte bit and an external interrupt is sensed by the edge detection circuitry, then the interrupt request is latched and the interrupt stays pending until the inte bit is set. the external latch of the external interrupt is cleared in the first part of the service routine (except for the low level interrupt which is not latched); therefore only one external interrupt pulse can be latched during t ilil and serviced as soon as the i-bit is cleared. 4.8 8-bit timer interrupt this timer can create two types of interrupts. a timer overflow interrupt occurs whenever the 8 bit timer rolls over from $ff to $00 and the enable bit tofe is set. a real time interrupt occurs whenever the programmed time elapses and the enable bit rtie is set. this interrupt vector to the interrupt service routine located at the address specified by the contents of memory location $3ff8 and $3ff9. for details see section 8. core timer . 4.8.1 16-bit timer interrupt there are five different timer interrupt flags that cause a 16-bit timer interrupt whenever they are set and enabled. the interrupt flags are in the timer status register (tsr), and the enable bits are in the timer control register1 (tcr1). any of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory location $3ff6 and $3ff7. for details see section 9. 16-bit programmable timer . freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
interrupts ambient exception interrupts mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required 4.9 ambient exception interrupts there are three different interrupt flags that cause an environmental exception interrupt whenever they are set and enabled. the interrupt flags are in the reset/interrupt status register (intsr), and the enable bits are in the interrupt control register (intcr). any of these interrupts vectors to the same interrupt service routine, located at the address specified by the contents of memory location $3ff4 and $3ff5. 4.10 high temperature interrupt htif ? high temperature interrupt flag this bit is set if the die temperature is higher than the upper trip point and cleared again if the die temperature falls below the lower trip point of the hti. 1 = the die temperature is higher than t htion 0 = the die temperature is lower than t htioff $0028 bit 7 654321bit 0 read: ulpm 0000 htie hvie lvie write: reset:00000000 figure 4-3 interrupt control register (intcr) $0029 bit 7 654321bit 0 read: rcon pc4cl 0 0 0 htif hvif lvif write: reset:na0000?00 figure 4-4 interrupt status register (intsr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required htie ? high temperature interrupt enable this bit enables/disables the high temperature interrupt. once this interrupt is acknowledged, the enable bit should be cleared and the high temperature interrupt flag should be monitored until the bit is cleared. 1 = high temperature interrupt enabled 0 = high temperature interrupt disabled 4.10.1 high voltage interrupt hvif ? high voltage interrupt flag this bit is set if the supply voltage v sup is higher than the upper trip point and cleared again if the voltage falls below the lower trip point of the hvi. 1 = the supply voltage is higher than v hvion 0 = the supply voltage is lower than v hioff hvie ? high voltage interrupt enable this bit enables/disables the high voltage interrupt. once this interrupt is acknowledged, the enable bit should be cleared and the high voltage interrupt flag should be monitored until the bit is cleared. 1 = high voltage interrupt enabled 0 = high voltage interrupt disabled 4.10.2 low voltage interrupt lvif ? low voltage interrupt flag this bit is set if the supply voltage v sup is lower than the lower trip point and cleared again if the voltage rises above the upper trip point of the lvi. 1 = the supply voltage is lower than v lvion 0 = the supply voltage is higher than v lvioff freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
interrupts keyboard interrupts mc68hc(8)05pv8/a ? rev. 1.9 technical data interrupts nondisclosure agreement required lvie ? low voltage interrupt enable this bit enables/disables the low voltage interrupt. once this interrupt is acknowledged, the enable bit should be cleared and the low voltage interrupt flag should be monitored until the bit is cleared. 1 = low voltage interrupt enabled 0 = low voltage interrupt disabled 4.10.3 power driver short circuit interrupt there are two different interrupt flags that cause a power driver short circuit interrupt whenever they are set and enabled. the interrupt flags are located in the port c status register, and the enable bits are located in the port c configuration register 1. any of these interrupts vector to the same interrupt service routine, located at the address specified by the contents of memory location $3ff4 and $3ff5. for details see 7.6 port c (high voltage port) . 4.11 keyboard interrupts when configured as input pins, pa0 ? 7 provide a wired-or keyboard interrupt facility and generate an interrupt provided the interrupt enable bits (palie or pahie) in the port a configuration register are set. the interrupt vector for this interrupt is located at $3ff2 and $3ff3. further information on the keyboard interrupt facility can be found in 7.4 port a . 4.12 port c contact sense interrupt there is an interrupt flag that causes a contact sense interrupt whenever it is set and enabled. this interrupt flag is a wired-or of the active contact sense inputs. the interrupt flag is located in the port c status register, and the enable bit is located in the port c configuration register 1. this interrupt vectors to the memory location $3ff0 and $3ff1. whenever a pcxcs bit is set, but the corresponding pin is not configured freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 interrupts nondisclosure agreement required as an output, the signal for the corresponding csdx bit, and therefore for the contact sense interrupt, is derived from the high-voltage input circuit. for details see 7.6 port c (high voltage port) . 4.13 stop and wait modes all modules that are capable of generating interrupts in stop or wait mode can only do so when configured properly. the i-bit is automatically cleared when stop or wait mode is entered. environmental exception interrupts and interrupts detected on port a and port c are recognized in stop or wait modes. on 68hc05pv8a, when ultra low power mode is selected by setting the ulpm bit, there will be no lvi, hvi, hti even if all conditions for an asserted interrupt are beeing met. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data resets nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5.4 external reset (reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.6 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.7 computer operating properly reset (copr). . . . . . . . . . . . . . 82 5.8 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.9 disabled stop instruction reset . . . . . . . . . . . . . . . . . . . . . . .84 5.10 high temperature reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.11 high voltage reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.12 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.13 operation in stop and wait mode . . . . . . . . . . . . . . . . . . . .85 5.14 clock monitor reset (cmr) . . . . . . . . . . . . . . . . . . . . . . . . . . .85 5.14.1 clock monitor in stop mode . . . . . . . . . . . . . . . . . . . . . . . 86 5.2 introduction the mcu can be reset from nine sources: one external input and eight internal restart conditions. the reset pin is an input with a schmitt trigger. all the internal peripheral modules are reset by the internal reset signal (rst). refer to figure 5-2 for reset timing details. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 resets nondisclosure agreement required 5.3 reset status register (rsr) this register contains eight flags that show the source of the last reset. a power-on reset sets the por bit in the system control register and clears all other bits in the reset status register. all bits can be cleared by writing a one to the corresponding bit. uncleared bits remain set as long as they are not cleared by a power-on reset or by software. pinr ? external reset bit 1 = last reset caused by external reset pin (reset ) 0 = no pin reset since pinr was cleared by software or por stopr ? illegal stop instruction reset bit indicates the last reset was caused by a disabled stop instruction. 1 = last reset caused by a disabled stop instruction 0 = no illegal stop instruction since stopr was cleared by software or por copr ? cop (computer operating properly) reset bit 1 = last reset caused by cop 0 = no cop reset since copr was cleared by software or por ilinr ? illegal instruction reset bit 1 = last reset caused by an instruction fetch from an illegal address 0 = no illegal instruction fetch reset since ilinr was cleared by software or por cmr ? clock monitor reset bit 1 = last reset caused by the clock monitor due to a failure on system clock or system clock is back. refer to rcon status bit in the interrupt status register 0 = no clock monitor reset since cmr was cleared by software or por $002a bit 7 654321bit 0 read: pinr stopr copr ilinr cmr htr hvr lvr write: por:00000000 figure 5-1 reset status register (rsr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
resets external reset (reset) mc68hc(8)05pv8/a ? rev. 1.9 technical data resets nondisclosure agreement required htr ? high temperature reset bit 1 = last reset caused by high temperature detect circuitry 0 = no high temperature reset since htr was cleared by software or por hvr ? high voltage reset bit 1 = last reset caused by high voltage detect circuitry 0 = no high voltage reset since hvr is cleared by software or por lvr ? low voltage reset bit 1 = last reset caused by low voltage detect circuitry 0 = no low voltage reset since lvr was cleared by software or por note: if the cause of an environmental reset only lasts for a short time and if there is an external capacitor on the reset pin, the corresponding bit in the reset status register may be set without occurrence of a reset. 5.4 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input generates the rst signal and resets the cpu and peripherals. activation of the rst signal is generally referred to as reset of the device, unless otherwise specified. the reset pin can also act as an open drain output. it is pulled to a low state by an internal pull-down that is activated by any reset source. this reset pull-down device is asserted until the internal reset source is deasserted and the reset is internally recognized. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 resets nondisclosure agreement required 5.5 internal resets the eight internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector, clock-monitor, the high temperature reset, high voltage reset, low-voltage reset, and the disabled stop instruction. when forcing reset externally to v dd , all temperature, voltage and clock-monitor dependent reset sources are disabled. in this case, the internal pull-down device tries to pull down the pin until the next recognized internal reset, which leads to some power-consumption. 5.6 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of t porl after the oscillator becomes active. see figure 5-2 for details. t porl is 4064 internal processor clock cycles. the por generates the rst signal which resets the cpu. if any other reset function is active at the end of this t porl delay, the rst signal remains in the reset condition until the other reset condition(s) ends. por activates the reset pin pull-down device connected to the pin. vdd must drop below v por in order for the internal por circuit to detect the next rise of v dd . internal resets reset pin vdd internal reset logic internal pullup freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
resets power-on reset (por) mc68hc(8)05pv8/a ? rev. 1.9 technical data resets nondisclosure agreement required figure 5-2 reset and por timing diagram pch pcl osc1 2 reset internal address bus 1 3ffe 3fff v dd t porl t cyc t rl internal data bus 1 3ffe 3ffe 3ffe 3ffe new pc 3fff notes: 1. internal timing signal and bus information not available externally. 2. osc1 line is not meant to represent frequency. i t is only used to represent time. 3. the next rising edge of the internal processor clock fol lowing the rising edge of reset initiates the reset sequence. 4. v dd must fall to a level lower than v por in order to be recognized as a power on reset. 3 new new op code pcl pch new pc new pc op code new pc 0v v dd > v por 4 internal processor clock 1 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 resets nondisclosure agreement required 5.7 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time-out, an internal reset is generated to reset the mcu. regardless of an internal or external reset, the mcu comes out of a cop reset according to the pin conditions that determine mode selection. the cop reset function is enabled or disabled by the mor[cope] bit and is verified during production testing. the cop watchdog reset activates the internal pull-down device connected to the reset pin. the window cop function can be enabled via the wcop bit in the system control register. this bit is a write once bit, e.g. the wcop feature stays enabled until the next system reset. in case of wcop bit enabled, the cop timer is only reset when the write to the copen bit in the mask option register occurs in the second half of the cop watchdog time. a write in the first half causes a system reset with the copr bit set. the phase of the cop timer can be monitored via the wcp (window cop phase) in the system control register. a 0 indicates that writing to the mor bit causes system reset. a 1 indicates that writing to the mor bit causes a reset of the cop timer cycle. 5.7.1 resetting the cop a cop reset is prevented by writing a 0 to the copr bit. this action resets the counter and begin the time-out period again. the copr bit is bit 0 of address $3ff0. a read of address $3ff0 returns user data programmed at that location. 5.7.2 cop during wait mode the cop continues to operate normally during wait mode. the system should be configured to pull the device out of wait mode periodically and reset the cop by writing to the copr bit to prevent a cop reset. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
resets computer operating properly reset (copr) mc68hc(8)05pv8/a ? rev. 1.9 technical data resets nondisclosure agreement required 5.7.3 cop during stop mode when the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter is reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter is held in reset during the 4064 cycles of start up delay. if any operable interrupt is used to exit stop mode, the cop counter is not reset during the 4064 cycle start-up delay and has the number of cycles already counted when control is returned to the program. 5.7.4 cop watchdog timer considerations the cop watchdog timer is active in user mode if enabled by the copen bit in the mask option register. if the cop watchdog timer is selected, any execution of the stop instruction (either intentional or inadvertent due to the cpu being disturbed) causes the oscillator to halt and prevent the cop watchdog timer from timing out. therefore, it is recommended that the stop instruction should be disabled if the cop watchdog timer is enabled. if the cop watchdog timer is selected, the cop resets the mcu when it times out. therefore, it is recommended that the cop watchdog be disabled for a system that must use the wait mode for periods longer than the cop time-out period. 5.7.5 cop register the cop register is shared with the msb of the contact sense interrupt vector as shown in figure 5-3 . reading this location returns whatever user data has been programmed at this location. writing a 0 to the copr bit in this location clears the cop watchdog timer. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 resets nondisclosure agreement required 5.8 illegal address reset an illegal address reset is generated when the cpu attempts to fetch an instruction from either unimplemented address space ($0100 to $017f, $0200 to $1fff) monitor rom ($3f00 to $3fef) or i/o address space ($0000 to $003f). the illegal address reset activates the internal pull-down device connected to the reset pin. 5.9 disabled stop instruction reset when the mask option is selected to disable the stop instruction, execution of a stop instruction results in an internal reset. this activates the internal pull-down device connected to the reset pin. 5.10 high temperature reset the internal high temperature (htr) reset is generated when the die temperature rises above the high temperature threshold t hton . this condition remains active until the temperature falls below the threshold t htoff . this reset can be disabled by using a mask option. $3ff0bit 7654321bit 0 read: write: copr reset: figure 5-3 cop watchdog timer location register (copr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
resets high voltage reset mc68hc(8)05pv8/a ? rev. 1.9 technical data resets nondisclosure agreement required 5.11 high voltage reset the internal high voltage (hvr) reset is generated when the supply voltage v sup rises above the high voltage reset threshold v hvron . this condition remains active until the supply voltage falls below the threshold v hvroff . this reset can be disabled by using a mask option. 5.12 low voltage reset the internal low voltage (lvr) reset is generated when the supply voltage v dd falls below the low voltage threshold v lvron . this condition remains active until the voltage rises above the threshold v lvroff or a proper power-on sequence occurs. 5.13 operation in stop and wait mode if enabled, all reset sources remain active during stop and wait. any reset source can bring the mcu out of stop or wait modes. since no instructions are executed in wait or stop mode the illegal address reset and the stop disabled reset cannot become active in stop or wait mode. since the core timer is not active in stop mode, the cop reset cannot become active in stop mode. on 68hc05pv8a, generation of hvr and htr are suppressed if the ultra low power mode is selected by setting the ulpm bit. 5.14 clock monitor reset (cmr) the clock monitor reset is based on an internal rc time delay. if no mcu clock edges are detected within this rc time delay, the clock monitor can optionally generate a system reset. the system clock is then automatically switched to an on-chip rc oscillator. the clock monitor function is enabled via a mask option bit. clock monitor is used as a freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 resets nondisclosure agreement required backup for the cop system. because the cop needs a clock to function it is disabled when the clock stops. therefore, the clock monitor system can detect clock failures not detected by the cop system. semiconductor wafer processing causes variations of the rc timeout values between individual devices. a processor clock frequency below 10 khz is detected as a clock monitor error. a processor clock frequency of 400 khz or more prevents clock monitor errors. using the clock monitor when the processor clock is below 400 khz is not recommended. the oscillator used for deriving the system clock can be determined by the rcon bit in the interrupt status register. 5.14.1 clock monitor in stop mode if stop mode is entered, the clock monitor function is frozen. if the device is woken from stop mode, it continues to use the same oscillator as before entering stop. for the stop mode recovery time of 4064 clock cycles, the clock monitor function is also suspended. if the device uses an external oscillator before entering stop mode and this oscillator breaks during stop, the device will no longer restart. $0029 bit 7 654321bit 0 read: rcon pc4cl 0 0 0 htif hvif lvif write: reset:u0000000 figure 5-4 interrupt status register (intsr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data operating modes nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.4 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 6.5.1.1 ultra low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5.2 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.2 introduction the normal operating mode of the mc68hc(8)05pv8/a is user (or single chip) mode. there is also a monitor mode, primarily for programming and evaluation purposes. in addition to these modes, there are two low power modes which may be entered and exited at will from user mode: stop and wait. table 6-1 shows the conditions required to enter the modes of operation on the rising edge of reset , where vtst = 2 x vdd. table 6-1 operating mode entry conditions irq pb0 mode vss to vdd vss to vdd user vtst vdd monitor freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 operating modes nondisclosure agreement required 6.3 user mode intended mode of operation for executing user firmware. 6.4 monitor mode used for programming the on-chip program or data eeprom (68hc805pv8) and data eeprom (68hc05pv8) if desired. 6.5 low power modes the mc68hc(8)05pv8/a is capable of running in one of several low-power operational modes. the wait and stop instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. the flows of the stop and wait modes are shown in figure 6-2 . 6.5.1 stop mode the stop instruction places the mcu in its lowest power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer (and cop watchdog timer) operation. during stop mode, the core timer interrupt flags and interrupt enable bits of the ctcsr register are cleared by internal hardware to remove any pending timer interrupt requests and to disable any further timer interrupts. the timer pre-scaler is also cleared. the i bit in the ccr is cleared to enable external interrupts. all other registers, including the remaining bits in the ctcsr, and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of the stop mode only by an external interrupt or reset . the stop instruction can be disabled by a mask option. when disabled, the stop instruction causes a system reset. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
operating modes low power modes mc68hc(8)05pv8/a ? rev. 1.9 technical data operating modes nondisclosure agreement required 6.5.1.1 ultra low power mode the ultra low power mode is only available on the 68hc05pv8a. it is a submode to stop mode. the ulpm bit in the interrupt control register influences the onchip analogue circuits. on setting the ulpm bit, pc0 .. pc4 is forced to input state, pc5/6 is switched off, opamp is debiased, downscaler, power supply and die temperature monitors are disabled. it is mandatory to set the ulpm bit in the last instruction prior to executing the stop instruction and should be reset immediately after recovering from stop to utilize the ultra low power mode. when the mcu is stopped, the main voltage regulator is switched off and the mcu is supplied by a standby regulator. on any interrupt or reset, the main regulator is switched on again and the normal stop mode recovery procedure is started as soon as vdd has reached the low voltage reset threshold. 6.5.2 stop recovery the processor can be brought out of the stop mode by an external interrupt, an environmental exception interrupt, a walk-up interrupt or reset . see figure 6-1 . freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 operating modes nondisclosure agreement required figure 6-1 stop recovery timing diagram 3ffe 3ffe 3ffe 3ffe 3fff internal address bus internal clock irq 3 irq 2 reset osc1 1 t ilch 4064 t cyc reset or interrupt vector fetch (reset shown) t lih t rl notes: 1. represents the internal gating of the osc1 pin. 2. irq pin edge-sensitive mask option or port a pin. 3. irq pin level and edge sensitive mask option. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
operating modes wait mode mc68hc(8)05pv8/a ? rev. 1.9 technical data operating modes nondisclosure agreement required figure 6-2 stop and wait flowcharts 6.6 wait mode the wait instruction places the mcu in a low-power consumption mode. all cpu action is suspended, but the core timer, the 16-bit timer (controlled by toff bit) and the pwm will or can remain active. an interrupt, if enabled, from the core timer or any peripheral still active in wait mode causes the mcu to exit wait mode. y y y y y n n n n stop wait irq port a or c reset oscillator active timer clock active processor clocks stopped stop oscillator and all clocks clear i bit 16b timer, core timer interrupt n y hvi, lvi restart processor clock turn on oscillator wait for time delay to stabilize 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine or hvr or lvr reset or hvr or lvr irq port a or c hvi, lvi freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 operating modes nondisclosure agreement required during wait mode the i bit in the ccr is cleared to enable interrupts. all other registers, memory and input/output lines remain in their previous state. the core timer may be enabled to allow a periodic exit from the wait mode. wait mode consumes more power than stop mode. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 7. input/output ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.3 general input/output programming . . . . . . . . . . . . . . . . . . . . . 94 7.4 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7.4.1 port a keyboard interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.4.2 port a pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.4.3 port a voltage reference for a/d converter. . . . . . . . . . . . 96 7.4.4 port a configuration register . . . . . . . . . . . . . . . . . . . . . . . 97 7.4.5 port a interrupt status register . . . . . . . . . . . . . . . . . . . . . 98 7.4.6 operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.5 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.1 port b timer channels and xor function . . . . . . . . . . . . 100 7.5.2 port b pwm channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 7.5.3 i/o configuration register. . . . . . . . . . . . . . . . . . . . . . . . . 101 7.6 port c (high voltage port) . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.6.1 port c timer channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.2 port c pwm channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.6.3 port c contact sense circuitry . . . . . . . . . . . . . . . . . . . . . 103 7.6.4 port c iso9141 interface . . . . . . . . . . . . . . . . . . . . . . . . . 106 7.6.5 port c low side driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 7.6.6 port c configuration register 0 . . . . . . . . . . . . . . . . . . . . 109 7.6.7 port c configuration register 1 . . . . . . . . . . . . . . . . . . . . 113 7.6.8 port c status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.6.9 mftest register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required 7.2 introduction in single chip mode there are 20 lines arranged as one 8-bit i/o port (port a), one 5-bit i/o port (port b), and one 7-bit high-voltage i/o port (port c). the i/o ports are programmable as either inputs or outputs under software control of the data direction registers (see 7.3 general input/output programming ). port a is shared with a/d channels. ports b and c are shared with timer and pwm channels. port c comprises 5 lines with contact sensors and 2 lines with low side drivers. 7.3 general input/output programming bidirectional port lines may be programmed as an input or an output under software control. the direction of the pins is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logical zero (see table 7-1 and figure 7-1 ). at power-on or reset, all ddrs are cleared, thus configuring all port pins as inputs. reset does not affect the state of the data bits, thus after power-on reset their state is unknown. the data direction registers are capable of being written to or read by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. table 7-1 i/o pin functions r/w (1) ddr i/o pin function 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. 1. r/w is an internal signal freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port a mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required figure 7-1 port i/o circuitry note: to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register. note: if the i/o pin is an input and a read-modify-write (rmw) instruction is executed, the i/o pin will be read into the hc05 cpu and the computed result will then be written to the data latch. 7.4 port a port a is an 8-bit bidirectional port (pa0 ? 7) with interrupt capability, shared with the a/d converter (an1 ? 6, vrefl, vrefh). the port a data register is located at $0000 and the data direction register (ddr) at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. when the a/d converter is turned on, one of the channels an1 ? 6 may be selected through the a/d status and control register for conversion. the input lines of port a include software programmable pull-up resistors. data direction register bit latched output data bit i/o pin input reg bit input i/o output internal hc05 connections freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required 7.4.1 port a keyboard interrupt the keyboard interrupt consists of 8 individual edge-sensitive interrupts with 8 interrupt flags. the keyboard interrupt is generated by a logical or function of the 8 interrupt flags. the interrupt inputs are connected to pa0 ? 7. all interrupts are maskable. if the interrupt mask bit (i bit) in the condition code register is set, all interrupts are disabled. the interrupts are split in two groups of four lines each (pa0 ? 3 and pa4 ? 7). all interrupts of one group can be simultaneously masked by the corresponding paie bits in the port a configuration register. the trigger edges of the interrupt lines are selectable for each group with the edge bits in the port a configuration register. the port a interrupt status register indicates which interrupt request is pending. 7.4.2 port a pull-up resistors the pa0 ? 7 input lines have internal pull-up resistors. the port a lines form two groups with four lines each (pa0 ? 3 and pa4 ? 7). all pull-up s of one group can be switched on with the pulen or puhen bits of the port a configuration register by resetting the bit to 0. they are disabled when the enable bit is set to 1 when a line is configured as output. 7.4.3 port a voltage reference for a/d converter the lines pa0 and pa7 can be connected to the reference inputs for the a/d converter (vrefl and vrefh). in order to connect the reference inputs, the corresponding vrhen or vrlen bits of the port a configuration register have to be set. in addition, the corresponding lines (pa0 or pa7) must be configured as inputs. the pull-up resistor should be disabled when a line is used as a/d input or a/d reference channel. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port a mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required 7.4.4 port a configuration register vrhen ? enable a/d high reference channel those bits connect the pa7 pin with the a/d high reference channel. 1 = a/d high reference channel connected to external vrefh. 0 = a/d high reference channel connected to internal voltage supply. puhen ? pa4 ? 7 pull-up resistor enable higher nibble this bit disables/enables the pull-up resistors of the pa4 ? 7 pins. 1 = pa4 ? 7 pull-up resistors disabled 0 = pa4 ? 7 pull-up resistors enabled edgeh ? pa4 ? 7 interrupt edge higher nibble this bit selects the trigger edges of the interrupt lines pa4 ? 7. 1 = rising edge sensitive 0 = falling edge sensitive pahie ? pa4 ? 7 interrupt enable higher nibble this bit disables/enables the pa4 ? 7 pins as an interrupt group. 1 = pa4 ? 7 interrupt enabled 0 = pa4 ? 7 interrupt disabled pulen ? pa0 ? 3 pull-up resistor enable lower nibble this bits disables/enables the pull-up resistors of the pa0 ? 3 pins. 1 = pa0 ? 3 pull-up resistors disabled 0 = pa0 ? 3 pull-up resistors enabled edgel ? pa0 ? 3 interrupt edge lower nibble this bit selects the trigger edges of the interrupt lines pa0 ? 3. 1 = rising edge sensitive 0 = falling edge sensitive $0020 bit 7 654321bit 0 read: vrhen puhen edgeh pahie pulen edgel palie vrlen write: reset:00000000 figure 7-2 port a configuration register (pacfg) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required palie ? pa0 ? 3 interrupt enable lower nibble this bit disables/enables the pa0 ? 3 pins as interrupt group. 1 = pa0 ? 3 interrupt enabled 0 = pa0 ? 3 interrupt disabled vrlen ? enable a/d low reference channel this bit connects the pa0 pin with the a/d low reference channel. 1 = a/d low reference channel connected to external vrefl. 0 = a/d low reference channel connected to internal ground. 7.4.5 port a interrupt status register paif0 ? 7 ? port a interrupt flags these flags indicate which of the port a interrupt requests is pending. the 8 interrupt flags can be reset individually if a 1 is written to the bit position. 1 = flag set when corresponding transition is sensed (if interrupt enabled). writing a 1 clears the flag 0 = no interrupt. writing a 0 has no effect 7.4.6 operational amplifier pins pa4 ? 6 are connected to an operational amplifier. the operational amplifier is intended for amplifying small signals over vss to increase the resolution of the a/d converter. the output stage of this operational amplifier is asymmetrical and thus optimized for driving loads to vss while keeping the quiescent current low. the output of the operational amplifier is connected to channel 4 of the a/d converter. the amplifier is enabled by the i/o configuration register bit6. as long as iocfg bit6 is 0, the presence of the operational amplifier is without any effect. if the opamp is enabled, first ensure that the pa4 is switched to input mode. $0024 bit 7 654321bit 0 read: paif7 paif6 paif5 paif4 paif3 paif2 paif1 paif0 write: reset:00000000 figure 7-3 port a interrupt status register (paisr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port a mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required note: pull-up resistors on pa4 ? 6 should be disabled when using the operational amplifier. figure 7-4 operational amplifier figure 7-5 typical application: positive vgain amplifier keep v in limited between v ss and v dd for precise measurements, r1 + r2 should be in the range of 50k ? and the v out should not reach v dd external loads should be connected to ground, due to small current sinking capability. in case of v in x gain >= v dd (i.e. the output of the operational amplifier cannot follow the input anymore) channel 6 (input) should be converted to read the input voltage v in directly. pa6 pa5 pa4 + ? iocfg bit6 pa6 pa5 pa4 + ? vss m v in to a/d shunt resistor r2 r1 a gain = r2 + r1 r1 v out freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required 7.5 port b port b is a 5-bit bidirectional port, shared with timer and pwm channels (tcap, tcmp, pwm). an xor function is provided for one timer capture channel. the port b data register is at $0001 and the data direction register (ddr) is at $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.5.1 port b timer channels and xor function the port pins pb0 ? pb3 are shared with the 16-bit timer channels (tcap1 ? 2, tcmp1 ? 2). the timer capture channel tcap1 can be driven by the xor of two channels if txor bit in the i/o configuration register is set (see figure 7-6 ).tcap1 status can be read by the cpu by polling bit 5 of the port b data register. figure 7-6 mapping ports to timer capture channels tcap1 pb0 pb0ic 0 1 pb2 pc2 pb2ic 0 1 txor 0 1 capture channel 1 capture channel 2 from pc0 or c4 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port b mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required 7.5.2 port b pwm channel the port pin pb4 is shared with the pwm channel. in order to connect this pin to the pwm channel, the corresponding bit pwm4 of the i/o configuration register must be set. 7.5.3 i/o configuration register txor ? timer exor enable this bit enables the exor of the tcap1 channel 1 = exor enabled 0 = exor disabled opamp ? enable operational amplifier this bit enables the operational amplifier on pa6 1 = opamp enabled 0 = opamp disabled pb4pw ? pb4 pwm enable this bit enables the pb4 pin as pwm output. 1 = pb4 pwm enabled. pbdd4 bit must be set in order to drive the output 0 = pb4 pwm disabled pb3oc ? pb3 output compare enable this bit enables the pb3 pin for output compare channel 2. 1 = pb3 output compare channel 2 enabled. pbdd3 bit must be set in order to drive the output 0 = pb3 output compare channel 2 disabled $0021 bit 7 654321bit 0 read: txor opamp pb4pw pb3oc pb2ic pb1oc pb0ic write: reset:00000000 figure 7-7 i/o configuration register (iocfg) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required pb2ic ? pb2 input capture enable this bit enables the pb2 pin to drive the input capture channel 2. 1 = pb2 drives the input capture channel 2 0 = pc2 drives the input capture channel 2 pb1oc ? pb1 output compare enable this bit enables the pb1 pin for output compare channel 1. 1 = pb1 output compare channel 1 enabled. pbdd1 bit must be set in order to drive the output 0 = pb1 output compare channel 1disabled pb0ic ? pb0 input capture enable this bit enables the pb0 pin to drive the input capture channel 1. 1 = pb0 drives the input capture channel 1 0 = pc0 or pc4 drives the input capture channel 1 7.6 port c (high voltage port) port c is a 7-bit multifunctional and bidirectional port (pc0 ? 6) with high voltage capability. the port is shared with timer and pwm channels (tcap, tcmp, pwm) and provides a special contact sense feature with interrupt capability. in addition, port c comprises a low ohmic two channel low side driver with internal zener diode turn-off for switching inductive loads. the port c data register is at $0002 and the data direction register (ddr) is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the pc0 ? 4 to high voltage inputs, pc5 and pc6 are switched to the off state. writing a one to a ddr bit sets the corresponding port bit to output or contact sense mode. the port c pins pc5 ? 6 are open drain outputs only without internal pull-ups. the voltage levels of pc0 ? 4 i/o signals are related to the v sup and v ss levels respectively. pc5 ? 6 have an additional power supply pin for vss (pvss) to which the low side drivers relate. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required 7.6.1 port c timer channels the port pins pc0 ? 5 are shared with the 16-bit timer channels (tcap1 ? 2, tcmp1 ? 2). 7.6.2 port c pwm channel the port pins pc0, 4 ? 6 are shared with the pwm channel. in order to connect those pins, please refer to 7.6.6 port c configuration register 0 for details. 7.6.3 port c contact sense circuitry the port c pins pc0 ? 4 have a special contact sense circuit (see figure 7-8 , figure 7-9 , figure 7-10 ). this feature allows, for example, the monitoring of mechanical contacts in automotive applications (switch monitor). figure 7-8 pc0 contact sense circuitry contact sense csdt pc0 data ddr i pin csen&data& ddrc interrupt r ext vsup vss freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required figure 7-9 pc1 ? 3 contact sense circuitry figure 7-10 pc4 contact sense circuitry 68hc(8)05pv8 contact sense contact sense csdt pc1 ? 3 data ddr i pin csen&data &ddrc interrupt r ext csen&data&ddrc vsup vss contact sense csdt pc4 data ddr i pin interrupt r ext csen&data&ddrc isomode vsup vss freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required figure 7-11 pc4 circuitry 68hc05pv8a port pin pc0 comprises a circuit that senses the outside resistance r pin to vsup. pc4 has a different circuit, which senses the outside resistance r pin to vss (only on 68hc(8)05pv8). pc1, pc2 and pc3 have an universal one, which senses the outside resistance either to vss or to vsup, depending on the state of the corresponding data register bit. the contact sense circuitry is enabled by setting the corresponding bits pc4cs, pc3cs, pc2cs, pc1cs or pc0cs of the port c configuration register to 1. in addition, the pin has to be configured as an output by setting the corresponding ddr bit to 1 and the data bit to 0 (for r pin to vsup, e.g. external switch to vsup) or to 1 (for r pin to vss, e.g. external switch to vss). if the outside resistance r pin is lower than the specified value, the contact sense circuitry interprets this as a logical 1. the principal sense characteristic is given in figure 7-12 . the result of this sense operation is given by the bits csd4, csd3, csd2, csd1 and csd0 of the port c status register. csdt pc4 data ddr interrupt vss freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required figure 7-12 principal characteristic of the contact sense circuitry when setting pcxcs and clearing the corresponding ddr bit, the signal generated by the high voltage input block is used instead of the one of the contact sense block to drive the csd bits. the csd bits will in this case reflect a logical 1 if the corresponding input voltage is below hv il , and a logical 0 if the input voltage is above hv ih . a contact sense interrupt is generated if the status of any csd bit changes with the corresponding pcxcs bit set. the interrupt trigger occurs on both edges of the csd bit change and sets the csif flag in the port c status register. the interrupt can be masked by the csie bit of the port c configuration register. an external resistor has to be placed in serial to pc0-4 because of two reasons: limit internal power dissipation, internal substrate current injection may occur if the pin voltage is out of the supply voltage range. 7.6.4 port c iso9141 interface to use port c4 as an iso9141 physical interface, port c4 must be always programmed as an output. this automatically enables the biasing circuit for the iso9141 driver. furthermore, the isom bit in the port c configuration register 0 has to be set. this driver incorporates an overcurrent limitation circuit. because of excessive power dissipation 0 1 contact sense data bit outside resistance csd4 ? 0 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required the software should take care to switch off the driver as soon as possible whenever a short-circuit occurs. to detect such a condition the pc4cl (bit 6) in the interrupt status register should be polled. figure 7-13 interrupt status register (intsr) mc68hc(8)05pv8 (maskset j47d and j31d): pc4cl - port c4 in current limit mode 1 = current on pc4 exceeds limit 0 = current on pc4 below limit mc68hc05pv8a (maskset k20r): pc4cl - port c4 in current limit mode 1 = current on pc4 below limit 0 = current on pc4 exceeds limit if the timer input capture 1 is configured to port c4, the state of the pc4 pin is transfered to the timer module input capture, the input status can be polled by reading the tcap1 bit in the port b data register. 7.6.5 port c low side driver the port c pins pc5 ? 6 comprise of two low side driver channels which are shared with the pwm function. the channels can either be controlled directly by the data register or are linked to the pwm function (see 7.6.2 port c pwm channel ). the low side driver channels are open-drain outputs with an internal zener diode. the diode clamps the maximum output voltage and limits the turn-off time of inductive loads (see figure 7-14 ). $0029 bit 7 654321bit 0 read: rcon pc4cl 0 0 0 htif hvif lvif write: reset:na0/1000?00 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required figure 7-14 principle of port c low side driver a permanent external pin voltage above the minimum zener break-down voltage can destroy the driver. the low side drivers have a short circuit protection feature. whenever the drain current of the ldmos transistor exceeds a fixed value, the output is automatically switched off (i.e. the ldmos is in the high impedance state) and the corresponding short circuit flag is set (scif5 or scif6). if the scie5/6 bits are enabled, an interrupt occurs. as long as the scif5/6 bits are set, the output cannot be switched on. these bits are cleared by writing a logical 1 to the corresponding bit location. the outputs are also protected by a common over temperature detection. see figure 7-15 for details. vsup fast turn-off ldmos solenoid pvss pc5?6 zener diode freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required figure 7-15 short circuit diagnostic of port c low side driver 7.6.6 port c configuration register 0 isom ? driver mode of pc4 this bit selects the driver mode of pc4. the isom bit is without function on 68hc05pv8a. 1 = iso9141 compatible output (low side driver only) 0 = pc4 is a push-pull output pc6pw ? pc6 pwm enable this bit enables the pc6 pin as pwm output. 1 = pc6 pwm enabled. 0 = pc6 pwm disabled $0022 bit 7 654321bit 0 read: isom pc6pw pwms1 pwms0 pc3oc ts2 ts1 ts0 write: reset:0 0000000 figure 7-16 port c configuration register 0 (pccfg0) pc6 ? 5 sout port c data drive control overcurrent detection scif5/6 pvss freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required pwms1, pwms0 ? pwm select bits these bits select the output pin for the pwm on pc0, pc4 or pc5. pc3oc ? pc3 output compare enable this bit enables the pc3 pin for output compare channel 2. 1 = pc3 output compare channel 2 enabled. pc3 ddr bit must be set in order to drive the output 0 = pc3 output compare channel 2 disabled ts2, ts1, ts0 ? timer channel 1 select bits these bits select the input and output pins for the timer channel 1. note: if pc0, pc1, pc4 and pc5 are neither switched to pwm nor to timer output compare, the output states of these pins follow the states of their data register bits. table 7-2 pwm select pwms1 pwms0 pwm output at port c 0 0 none 01 pc0 10 pc4 11 pc5 table 7-3 timer channel 1 select ts2 ts1 ts0 output compare at pcx input capture at pcx 0 0 0 none, bit i/o pc0 0 0 1 none, bit i/o pc4 0 1 0 pc0 pc0 011 pc0 pc4 100 pc1 pc0 101 pc1 pc4 110 pc4 pc4 111 pc5 pc4 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required to enable either pwm or output compare function the corresponding ddr bit must be set to 1. if pwm and timer output compare functions are routed to the same pin, pc0 and pc4 would be connected to the output compare signal, pc5 would be connected to the pwm signal. for using the input capture be sure that the pb0ic bit in the i/o configuration register is set to 0, and the corresponding pin pc0 or pc4 is switched to input mode. pc4 may also be in the iso9141 compatible mode. for using the contact sense function, it is not recommended to route any special signal to the corresponding pins. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required figure 7-17 port c special signal routing pc0 pc2 pc4 pc1 pc3 pc5 pc6 pc6pw pwms1,0 pwm pc3oc toc2 ts2,1,0 ddrc, ts2,1,0, pws1,0 toc1 port c data 0 port c data 1 port c data 2 port c data 3 port c data 4 port c data 5 port c data 6 pb0 pb2 ts2,1,0 pb2oc pb0oc txor tic1 tic2 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required 7.6.7 port c configuration register 1 csie ? port c contact sense interrupt enable this bit enables contact sense interrupt of the lines pc4 ? 0. 1 = port c contact sense interrupt enabled 0 = port c contact sense interrupt disabled scie6 ? low side driver short circuit interrupt enable this bit enables short circuit interrupt of the low side driver pc6. 1 = low side driver short circuit interrupt enabled 0 = low side driver short circuit interrupt disabled scie5 ? low side driver short circuit interrupt enable this bit enables short circuit interrupt of the low side driver pc5. 1 = low side driver short circuit interrupt enabled 0 = low side driver short circuit interrupt disabled pc4cs ? pc4 contact sense enable this bit enables the pc4 contact sense circuitry. 1 = pc4 contact sense circuitry enabled 0 = pc4 contact sense circuitry disabled pc3cs ? pc3 contact sense enable this bit enables the pc3 contact sense circuitry. 1 = pc3 contact sense circuitry enabled 0 = pc3 contact sense circuitry disabled pc2cs ? pc2 contact sense enable this bit enables the pc2 contact sense circuitry. 1 = pc2 contact sense circuitry enabled 0 = pc2 contact sense circuitry disabled $0026 bit 7 654321bit 0 read: csie scie6 scie5 pc4cs pc3cs pc2cs pc1cs pc0cs write: reset:0 0000000 figure 7-18 port c configuration register 1 (pccfg1) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required pc1cs ? pc1 contact sense enable this bit enables the pc1 contact sense circuitry. 1 = pc1 contact sense circuitry enabled 0 = pc1 contact sense circuitry disabled pc0cs ? pc0 contact sense enable this bit enables the pc0 contact sense circuitry. 1 = pc0 contact sense circuitry enabled 0 = pc0 contact sense circuitry disabled 7.6.8 port c status register csif ? port c contact sense interrupt flag this flag indicates that a contact sense transition has occurred and an interrupt request is pending. the flag can be cleared by writing a 1 to it. 1 = flag set when a transition is sensed by the contact sense circuitry 0 = no interrupt scif6 ? low side driver short circuit interrupt flag this flag indicates a short circuit on pc6 is active and an interrupt request is pending. 1 = short circuit at the pc6 pin; pc6 is switched to high impedance 0 = no short circuit at the pc6 pin $0027 bit 7 654321bit 0 read: csif scif6 scif5 csd4 csd3 csd2 csd1 csd0 write: reset:0 0000000 figure 7-19 port c status register (pcstr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
input/output ports port c (high voltage port) mc68hc(8)05pv8/a ? rev. 1.9 technical data input/output ports nondisclosure agreement required scif5 ? low side driver short circuit interrupt flag this flag indicates a short circuit on pc5 is active and an interrupt request is pending. 1 = short circuit at the pc5 pin; pc5 is switched to high impedance 0 = no short circuit at the pc5 pin csd4 ? pc4 contact sense data this data bit represents the result of the pc4 contact sense circuitry. 1 = low resistance sensed (see figure 7-12 ), or input pc4 is 0. 0 = high resistance sensed csd3 ? pc3 contact sense data this data bit represents the result of the pc3 contact sense circuitry. 1 = low resistance sensed (see figure 7-12 ), or input pc3 is 0. 0 = high resistance sensed csd2 ? pc2 contact sense data this data bit represents the result of the pc2 contact sense circuitry. 1 = low resistance sensed (see figure 7-12 ), or input pc2 is 0. 0 = high resistance sensed csd1 ? pc1 contact sense data this data bit represents the result of the pc1 contact sense circuitry. 1 = low resistance sensed (see figure 7-12 ), or input pc1 is 0. 0 = high resistance sensed csd0 ? pc0 contact sense data this data bit represents the result of the pc0 contact sense circuitry. 1 = low resistance sensed (see figure 7-12 ), or input pc0 is 0. 0 = high resistance sensed freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 input/output ports nondisclosure agreement required 7.6.9 mftest register hvtoff ? disable of port c inputs this data bit controls the operation of the port c inputs 1 = port c high voltage inputs (pc0 - pc4) disabled 0 = port c high voltage inputs enabled vscal ? disable of v sup scaler circuit this data bit controls the operation of the v sup scaler circuit 1 = v sup scaler disabled, this mode saves power consumption 0 = v sup scaler enabled, v sup can be measured using the a/d converter channel 7 lsoff ? low side drivers off this data bit controls the operation of pc5-6 and the temperature sensor block 1 = pc5-6 and temperature block disabled to minimize power consumption 0 = pc5-6 and and temperature block enabled vt2, vt1, vt0 ? voltage regulator trimming bits refer to 12.5 trimming the voltage regulator . $002f bit 7 654321bit 0 read: hvtoff vscal lsoff vt2 vt1 vt0 write: reset:0 0000000 figure 7-20 mftest register (mftest) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data core timer nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 8. core timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.3.1 core timer status & control register (ctscr) . . . . . . . .119 8.3.2 computer operating properly (cop) watchdog reset. . . 121 8.3.3 core timer counter register (ctcr). . . . . . . . . . . . . . . . 121 8.4 core timer during wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.5 core timer during stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 8.2 introduction the core timer for this device is a 15-stage multi-functional ripple counter. the features include timer over flow, power-on reset (por), real time interrupt (rti), and cop watchdog timer. as seen in figure 8-1 , the timer is driven by the output of the clock select circuit followed by a fixed divide by four pre-scaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. two additional stages produce the por function after 4064 clks (if selected). the timer counter bypass circuitry (available only in test mode) is at this point in the timer chain. this circuit is followed by two more stages, with the resulting clock (f op /16384) driving the real time interrupt circuit. the rti circuit consists of three divider stages with a 1 of 4 selector. the output of the rti circuit is further divided by eight to drive the mask optional cop watchdog timer circuit. the rti rate selector bits, and the freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 core timer nondisclosure agreement required rti and tof enable bits and flags are located in the timer status and control register at location $08. figure 8-1 core timer block diagram cop clear $9 tcr 7-bit counter interrupt circuit $08 tcsr rti select circuit overflow circuit detect cop watchdog timer ( 8) to reset logic to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcbp tcsr tcr internal processor clock tof rtif tofe rtie rt1 rt0 rrtif rtof timer control/status register timer counter register (tcr) 4 internal bus 8 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
core timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data core timer nondisclosure agreement required 8.3 registers 8.3.1 core timer status & control register (ctscr) the ctscr contains the timer interrupt flag, the timer interrupt enable bits, and the real time interrupt rate select bits. figure 8-2 shows the value of each bit in the ctscr when coming out of reset. tof ? timer over flow tof is a read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if tofe is set. reset clears tof. rtif ? real time interrupt flag the real time interrupt circuit consists of a three stage divider and a 1 of 4 selector. the clock frequency that drives the rti circuit is f op /2 13 (or f op /8192) with three additional divider stages giving a maximum interrupt period of about 250ms at a crystal frequency of 1 mhz. rtif is a read-only status bit and is set when the output of the chosen (1 of 4 selection) stage goes active. a cpu interrupt request will be generated if rtie is set. reset clears rtif. tofe ? timer over flow enable when this bit is set, a cpu interrupt request is generated when the tof bit is set. reset clears this bit. rtie ? real time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. $0008 bit 7 654321bit 0 read: tof rtif tofe rtie 00 rt1 rt0 write: rtof rrtif reset:00000011 figure 8-2 core timer status and control register (ctscr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 core timer nondisclosure agreement required rtof ? reset tof this bit always reads 0. setting this bit clears the timer overflow flag (tof). clearing this bit has no effect. rrtif ? reset rtif this bit always reads 0. setting this bit clears the real time interrupt flag (rtif). clearing this bit has no effect. rt1, rt0 ? real time interrupt rate select these two bits select one of four taps from the real time interrupt circuit. table 8-1 shows the available interrupt rates with several f op values. reset sets these rt0 and rt1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching an rtif could be missed or an additional one could be generated. to avoid problems the cop should be cleared before changing rti taps. table 8-1 rti rates rti rates at bus frequency f op specified: rt1:rt0 500 khz 1.000 mhz 2.000 mhz 2.4576 mhz ratio 00 32.768ms 16.384ms 8.192ms 6.667ms 2 14 /f op 01 65.536ms 32.768ms 16.384ms 13.333ms 2 15 /f op 10 131.072ms 65.536ms 32.768ms 26.667ms 2 16 /f op 11 262.144ms 131.072ms 65.536ms 53.333ms 2 17 /f op freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
core timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data core timer nondisclosure agreement required 8.3.2 computer operating properly (cop) watchdog reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 8-2 . if the cop circuit times out, an internal reset is generated and the normal reset vector is fetched. a cop time-out is prevented by clearing bit 0 of address $3ff0. when the cop is cleared, only the final divide by eight stage (output of the rti) is cleared. 8.3.3 core timer counter register (ctcr) the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. table 8-2 minimum cop reset times minimum cop reset bus frequency at f op specified: rt1:rt0 500 khz 1.000 mhz 2.000 mhz 2.4576 mhz ratio 00 229.376ms 114.689ms 57.344ms 46.666ms 7*2 14 /f op 01 458.752ms 229.376ms 114.689ms 93.333ms 7*2 15 /f op 10 917.504ms 458.752ms 229.376ms 186.666ms 7*2 16 /f op 11 1835.000ms 917.504ms 458.752ms 373.333ms 7*2 17 /f op $0009 bit 7 654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 8-3 core timer counter register (ctcr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 core timer nondisclosure agreement required the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted anytime during operation (other than por), the counter chain will be cleared. 8.4 core timer during wait the cpu clock halts during the wait mode but the core timer remains active. if the ctimer interrupts are enabled, then a ctimer interrupt will cause the processor to exit the wait mode. 8.5 core timer during stop the timer and the interrupt mask and enable flags are cleared when going into stop mode. when stop is exited by an external interrupt or an external reset the internal oscillator will restart, followed by an internal processor stabilization delay (t porl ). the timer is then cleared and the operation resumes. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 9. 16-bit programmable timer 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.3 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.1 counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3.2 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . 127 9.3.3 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . .129 9.3.4 timer control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.3.5 timer control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3.6 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.4 timer during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.5 timer during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required 9.2 introduction the mc68hc(8)05pv8/a has one 16-bit timer with two channels. the timer consists of a 16-bit free running counter driven by a fixed divide-by-four pre-scaler. this timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform. pulse widths can vary from several microseconds to many seconds. the output compare is improved so that it is now possible to link the two output compares to one output in order to generate pulses as short as e/4. refer to figure 9-1 for a timer block diagram. because the timer has a 16-bit architecture each specific functional segment is represented by two registers. these registers contain the high and low byte of that functional segment. generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. the i bit in the ccr should be set while manipulating both the high and low byte register of a specific timer function to ensure that an interrupt does not occur. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer introduction mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required figure 9-1 timer block diagram 68hc05 internal bus low byte high byte $14 $15 low byte high byte $10 $11 low byte high byte $16 $17 low byte high byte $12 $13 low byte high byte $18 $19 $1a $1b 4 internal bus clock internal timer bus oci1e tofie ici1e ici2e oci2e - - toff oc1f tof ic1f ic2f oc2f si1 si2 - tcap2 tcap1 tcr1 $1c tsr $1e clk21 iedg1 iedg2 folv1 olvl1 folv2 olvl2 tcmp1 q d clk12 c latch tcmp2 q d c latch tcr2 $1d output compare 1 output compare 2 input capture 1 input capture 2 8-bit buffer output compare output compare edge detect 1 edge detect 2 overflow detect 16-bit free running counter counter alternate register interrupt q d c latch q d c latch tcap2 tcap1 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required 9.3 registers 9.3.1 counter the key element in the programmable timer is a 16-bit free-running counter or counter register, preceded by a pre-scaler that divides the internal processor clock by four. the pre-scaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value. the double-byte free-running counter can be read from either of two locations, $18 ? $19 (counter register) or $1a ? $1b (counter alternate register). a read from only the least significant byte (lsb) of the free-running counter ($19, $1b) receives the count value at the time of the read. if a read of the free-running counter, or counter alternate register first addresses the most significant byte ($18, $1a), the lsb ($19, $1b) is transferred to a buffer. this buffer value remains fixed after the first msb read even if the user reads the msb several times. this buffer is accessed when reading the free-running counter or counter alternate register, lsb ($19 or $1b) and thus completes a read sequence of the total counter value. in reading either the free-running counter or counter alternate register, if the msb is read, the lsb must also be read to complete the sequence. the counter alternate register differs from the counter register in one respect: a read of the counter register msb can clear the timer overflow flag (tof). therefore, the counter alternate register can be read at any time without the possibility of missing timer overflow interrupts due to clearing of the tof. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required 9.3.2 output compare registers there are two output compare registers: output compare register 1 and output compare register 2. output compare registers can be used for several purposes such as controlling an output waveform or indicating when a period of time has elapsed. all bits are readable and writeable and are not altered by the timer hardware or reset. if the compare function is not needed the two bytes of the output compare register can be used as storage locations. 9.3.2.1 output compare register 1 the 16-bit output compare register 1 is made up of two 8-bit registers at locations $12 (msb) and $13 (lsb). the output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. if a match is found, the output compare flag oc1f (bit 5 of the timer status register ($1e)) is set and the corresponding output level olvl1 bit is clocked to tcmp1 output. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oci1e) is set. after a processor write cycle to the output compare register 1 containing the msb ($12), the output compare function is inhibited until the lsb ($13) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($13) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. the processor can write to either byte of the output compare register 1 without affecting the other byte. the output level (olvl1) bit is clocked to the output level register regardless of whether the output compare flag (oc1f) is set or clear. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required because the output compare flag oc1f and the output compare register 1 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function. the following procedure is recommended. write the high byte to the compare register 1 to inhibit further compares until the low byte is written. read the status register to arm the oc1f if it is already set. write the output compare register 1 low byte to enable the output compare 1 function with the flag clear. the purpose of this procedure is to prevent the oc1f bit from being set between the time it is read and the write to the corresponding output compare register. 9.3.2.2 output compare register 2 the 16-bit output compare register 2 is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the output compare register contents are compared with the contents of the free-running counter once every four internal processor clock cycles. if a match is found, the output compare flag oc2f (bit 3 of the timer status register ($1e)) is set and the corresponding output level olvl2 bit is clocked to tcmp2 output. the output compare register values and the output level bit should be changed after each successful comparison to establish a new elapsed time-out. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (oci2e) is set. after a processor write cycle to the output compare register 2 containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare function. the free-running counter is updated every four internal bus clock cycles. the minimum time required to update the output compare register is a function of the program rather than the internal hardware. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required the processor can write to either byte of the output compare register 2 without affecting the other byte. the output level (olvl2) bit is clocked to the output level register regardless of whether the output compare flag (oc2f) is set or clear. because the output compare flag oc2f and the output compare register 2 are undetermined at power-on, and are not affected by external reset, care must be exercised when initializing the output compare function. a procedure as recommended for compare register 1 should be followed. 9.3.3 input capture registers there are two identical input capture registers: input capture register 1 and input capture register 2. the two following sections describe these two registers. 9.3.3.1 input capture register 1 two 8-bit registers, which make up the 16-bit input capture register 1, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the tcap1 pin. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg1). reset does not affect the contents of the input capture register except when exiting stop mode. iedg1 ? capture on negative/positive edge 1 = capture on positive edge 0 = capture on negative edge an interrupt can also accompany a capture provided the corresponding interrupt enable bit, ici1e, is set. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter which is four internal bus clock cycles. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ic1f) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register most significant byte ($10), the counter transfer is inhibited until the least significant byte ($11) is also read. this characteristic causes the time used in the input capture software routine, and its interaction with the main program, to determine the minimum pulse period. a read of the input capture register lsb ($11) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.3.2 input capture register 2 two 8-bit registers, which make up the 16-bit input capture register 2, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition on the tcap2 pin. the level transition which triggers the counter transfer is defined by the corresponding input edge bit (iedg2). reset does not affect the contents of the input capture register except when exiting stop mode. iedg2 ? capture on negative/positive edge 1 = capture on positive edge 0 = capture on negative edge an interrupt can also accompany a capture provided the corresponding interrupt enable bit, ici2e, is set. the result obtained by an input capture will be one more than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required the free-running counter contents are transferred to the input capture register on each proper signal transition regardless of whether the input capture flag (ic2f) is set or clear. the input capture register always contains the free-running counter value that corresponds to the most recent input capture. after a read of the input capture register most significant byte ($14), the counter transfer is inhibited until the least significant byte ($15) is also read. this characteristic causes the time used in the input capture software routine, and its interaction with the main program, to determine the minimum pulse period. a read of the input capture register lsb ($15) does not inhibit the free-running counter transfer since they occur on opposite edges of the internal bus clock. 9.3.4 timer control register 1 ici1e ? input capture 1 interrupt enable 1 = interrupt enabled 0 = interrupt disabled ici2e ? input capture 2 interrupt enable 1 = interrupt enabled 0 = interrupt disabled oci1e ? output compare 1 interrupt enable 1 = interrupt enabled 0 = interrupt disabled toie ? timer overflow interrupt enable 1 = interrupt enabled 0 = interrupt disabled $001c bit 7 654321bit 0 read: ici1e ici2e oci1e toie oci2e toff write: reset:00000uu0 figure 9-2 timer control register 1 (tcr1) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required oci2e ? output compare 2 interrupt enable 1 = interrupt enabled 0 = interrupt disabled toff ? shut off timer 1 = timer is disabled. this can be used to save power if timer is not used 0 = timer is enabled 9.3.5 timer control register 2 iedg1 ? input edge value of input edge determines which level transition on tcap1 pin will trigger free running counter transfer to the input capture register 1. 1 = positive edge 0 = negative edge iedg2 ? input edge value of input edge determines which level transition on tcap2 pin will trigger free running counter transfer to the input capture register 2. 1 = positive edge 0 = negative edge clk21 ? output compare 2 clocks output latch 1 if this bit is set to 1, a successful compare of compare register 2 loads the olvl2 bit to the output latch 1. this feature can be used to get output pulses as short as e/4 while using only one interrupt. $001d bit 7 654321bit 0 read: iedg1 iedg2 clk21 0 olvl1 clk12 0 olvl2 write: folv1 folv2 reset: u u 0 0 u 0 0 u figure 9-3 timer control register 2 (tcr2) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required folv1 ? force output level 1 the folv1 bit always reads as zero. writing a zero at this position has no effect. writing a one at this position will force the olvl1 bit to the corresponding output level latch, thus appearing at pin tcmp1. note that the force output compare 1 does not affect the ocf1 bit of the status register. olvl1 ? output level 1 value of output level is clocked into output level register by the next successful output compare 1 and will appear on the tcmp1 pins. 1 = high output 0 = low output clk12 ? output compare 1 clocks output latch 2 if this bit is set to 1, a successful compare of compare register 1 loads the olvl1 bit to the output latch 2. this feature can be used to get output pulses as short a e/4 while using only one interrupt. folv2 ? force output level 2 the folv2 bit always reads as zero. writing a zero at this position has no effect. writing a one at this position will force the olvl2 bit to the corresponding output level latch thus appearing at pin tcmp2. note that the force output compare 2 does not affect the ocf2 bit of the status register. olvl2 ? output level 2 value of output level is clocked into output level register by the next successful output compare 2, and will appear on the tcmp2 pin. 1 = high output 0 = low output freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required 9.3.6 timer status register the timer status register is a read-only register containing timer status flags. ic1f ? input capture 1 flag 1 = flag set when selected polarity edge is sensed by input capture 1 edge detector 0 = flag cleared when tsr and input capture 1 registers low byte is accessed ic2f ? input capture 2 flag 1 = flag set when selected polarity edge is sensed by input capture 2 edge detector 0 = flag cleared when tsr and input capture 2 registers low byte is accessed oc1f ? output compare 1 flag 1 = flag set when output compare register 1 contents match the free-running counter contents 0 = flag cleared when tsr and output compare register 1 low byte are accessed tof ? timer overflow flag 1 = flag set when free-running counter transition from $ffff to $0000 occurs 0 = flag cleared when tsr and counter low register are accessed oc2f ? output compare 2 flag 1 = flag set when output compare register 2 contents match the free-running counter contents 0 = flag cleared when tsr and output compare register 2 low byte are accessed $001e bit 7 654321bit 0 read: ic1f ic2f oc1f tof oc2f si1 si2 0 write: reset:uuuuuuu0 figure 9-4 timer status register 1 (tsr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
16-bit programmable timer registers mc68hc(8)05pv8/a ? rev. 1.9 technical data 16-bit programmable timer nondisclosure agreement required si1 ? sample input 1 1 = bit set when input capture 1 input is sampled high while output compare register 1 matches the free running counter 0 = bit cleared when input capture 1 input is sampled low while output compare register 1 matches the free running counter si2 ? sample input 2 1 = bit set when input capture 2 input is sampled high while output compare register 2 matches the free running counter 0 = bit cleared when input capture 2 input is sampled low while output compare register 2 matches the free running counter accessing the timer status registers satisfies the first condition required to clear status bits. the remaining step is to access the registers corresponding to the status bit. a problem can occur when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time. without incorporating the proper precautions into software, the timer overflow flag could unintentionally be cleared if: 1. the timer status register is read or written when tof is set, and 2. the lsb of the free-running counter is read but not for the purpose of servicing the flag the counter alternate register contains the same value as the free-running counter; therefore this alternate register can be read at any time without affecting the timer overflow flag in the timer status register. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 16-bit programmable timer nondisclosure agreement required 9.4 timer during wait mode the cpu clock halts during wait mode but the timer keeps on running. if any reset is used to exit wait mode the counters are forced to $fffc. if interrupts are enabled a timer interrupt will cause the processor to exit wait mode. 9.5 timer during stop mode in stop mode the timer stops counting and holds the last count value if stop is exited by an interrupt. if any reset is used the counters are forced to $fffc. note: during stop, if at least one valid input capture edge occurs at the tcap pins, the input capture detect circuit is armed. this does not set any timer flags nor wake up the mcu, but when the mcu does wake up, there is an active input capture flag and data from the first valid edge that occurred during stop mode. if any reset is used to exit stop mode then no input capture flag or data remains even if a valid input capture edge occurred. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data analog to digital converter nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 10. analog to digital converter 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.3 a/d principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 a/d operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.5 internal and master oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 139 10.6 a/d registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.6.1 a/d status and control register (adscr) . . . . . . . . . . . . 140 10.6.2 a/d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.7 a/d during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 10.8 a/d during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 10.9 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.10 conversion accuracy definitions . . . . . . . . . . . . . . . . . . . . . . 144 10.10.1 transfer curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 10.10.2 monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.3 quantization error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.10.4 offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.5 gain scale error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.6 differential linearity error . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.7 integral linearity error. . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.10.8 total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 analog to digital converter nondisclosure agreement required 10.2 introduction the analog to digital converter system consists of a single 8-bit successive approximation converter and a channel multiplexer. there is one 8-bit result data register and one 8-bit status/control register. the reference supply can be switched by software either to the internal vdd and vss supplies or to external pins individually. an internal rc type oscillator is activated by the adrc bit in the a/d status and control register (adscr). this rc oscillator is used to provide a sufficiently high clock rate to the a/d when the bus speed is too low for the a/d to be accurate. additionally, the adon bit allows the user to save power by disconnecting the a/d when not in use. this is particularly useful to reduce current consumption (typically by 100 a) when going into wait mode. the a/d is ratiometric to the internal reference voltages vrefh and vrefl which can be derived from either vdd/vss or external pins. an input voltage equal to or greater than vrefh converts to $ff (full scale) with no overflow indication (if greater). an input voltage equal to vrefl converts to $00. for ratiometric conversions, the source of each analog input should use vrefh as the supply voltage and be referenced to vrefl. 10.3 a/d principle the a/d reference inputs are applied to a precision internal digital to analog converter. control logic drives this d/a and the analog output is successively compared to the selected analog input which was sampled at the beginning of the conversion time. the conversion is monotonic with no missing codes. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
analog to digital converter a/d operation mc68hc(8)05pv8/a ? rev. 1.9 technical data analog to digital converter nondisclosure agreement required 10.4 a/d operation the a/d is an 8-bit successive approximation register (sar) type a/d converter with continuous conversion per given channel. the result of a conversion is loaded into the read-only result data register and a conversion complete flag coco is set in the a/d status/control register. any write to the a/d status/control register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. at power-on or external reset both the adrc and adon bits are cleared. thus the a/d is disabled. each conversion takes 32 clock cycles which must be at a frequency equal to or greater than 1 mhz. a multiplexer allows the single a/d converter to select one of six external analog signals two internal signal sources and three internal reference sources. 10.5 internal and master oscillator if the mcu bus (e clock) frequency is less than 1.0 mhz, an internal rc oscillator (nominally 1.5 mhz) must be used for the a/d conversion clock. this selection is made by setting the adrc bit in the a/d status and control register to 1. when the internal rc oscillator is being used as the conversion clock three limitations apply: 1. the conversion complete flag (coco) must be used to determine when a conversion sequence has been completed, due to the frequency tolerance of the rc oscillator and its asynchronism with regard to the mcu bus clock. 2. the conversion process runs at the nominal 1.5 mhz rate but the conversion results must be transferred to the mcu result registers synchronously with the mcu bus clock so conversion time is limited to a maximum of one channel per bus cycle. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 analog to digital converter nondisclosure agreement required 3. if the system clock is running faster than the rc oscillator, the rc oscillator should be turned off, and the system clock used as the conversion clock. 10.6 a/d registers 10.6.1 a/d status and control register (adscr) the following paragraphs describe the function of the a/d status and control register. coco ? conversion complete this read-only status bit is set when a conversion is completed, indicating that the a/d data register contains valid results. this bit is cleared whenever the a/d status and control register is written and a new conversion automatically started, or whenever the a/d register is read. once a conversion has been started by writing to the a/d status and control register, conversions of the selected channel will continue every 32 cycles until the a/d status and control register is written again. in this continuous conversion mode, the a/d data register will be filled with new data, and the coco bit set, every 32 cycles. data from the previous conversion will be overwritten regardless of the state of the coco bit prior to writing. adrc ? rc oscillator on when adrc is set, the a/d section runs on the internal rc oscillator instead of the cpu clock. the rc oscillator requires a time t rcon to stabilize and results can be inaccurate during this time. see 10.5 internal and master oscillator . $000f bit 7 654321bit 0 read: coco adrc adon adtst ch3 ch2 ch1 ch0 write: reset: uuuuuuuu figure 10-1 a/d status and control register (adscr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
analog to digital converter a/d registers mc68hc(8)05pv8/a ? rev. 1.9 technical data analog to digital converter nondisclosure agreement required adon ? a/d on when the a/d is turned on (adon = 1), it requires a time t adon for the current sources to stabilize, and results can be inaccurate during this time. this bit turns on the charge pump. adtst this bit is for test purposes only. write only 0. ch3:0 ? channel select bit ch3, ch2, ch1 and ch0 form a four bit field which is used to select one of sixteen a/d channels. channels 8 ? 15 are used for internal reference points. the following table shows the signals selected by the channel select field. table 10-2. a/d clock selection adrc adon comments 0 0 rc oscillator off, a/d converter off. 0 1 rc oscillator off, a/d converter on. 10 rc oscillator on, a/d converter off. gives time for the rc osc to stabilize. 11 rc oscillator on, a/d converter on. a/d using rc osc clocks table 10-1 a/d channel assignments ch3 ch2 ch1 ch0 channel signal 0000 0 t j 0001 1 pa1 0010 2 pa2 0011 3 pa3 0100 4 pa4 0101 5 pa5 0100 6 pa6 0111 7 v sup / [100mv/bit] freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 analog to digital converter nondisclosure agreement required note: channel 0 and 7 ? 15 convert internal signals which cannot be accessed externally. 10.6.2 a/d data register one 8-bit result register is provided. this register is updated each time coco is set. 10.7 a/d during wait mode the a/d converter continues normal operation during wait mode. to decrease power consumption during wait it is recommended that both the adon and adrc bits in the a/d status and control registers be cleared if the a/d converter is not being used. if the a/d converter is in use and the system clock rate is above 1.0 mhz it is recommended that the adrc bit be cleared. as the a/d converter continues to function normally in wait mode the coco bit is not cleared. 1000 8 v refh 1001 9(v refh +v refl )/2 101010 v refl 1011 11 v refl 11xx12-15 v refl table 10-1 a/d channel assignments ch3 ch2 ch1 ch0 channel signal $000e bit 7 654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: uuuuuuuu figure 10-3 a/d data register (addr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
analog to digital converter a/d during stop mode mc68hc(8)05pv8/a ? rev. 1.9 technical data analog to digital converter nondisclosure agreement required 10.8 a/d during stop mode in stop mode the comparator and charge pump are turned off and the a/d ceases to function. any pending conversion is aborted. when the clocks begin oscillation upon leaving the stop mode, a finite amount of time passes before the a/d circuits stabilize enough to provide conversions to the specified accuracy. normally the delays built into the device when coming out of stop mode are sufficient for this purpose therefore no explicit delays need to be built into the software. although the comparator and charge pump are disabled in stop mode the a/d data and status/control registers are not modified. disabling the a/d prior to entering stop mode will not affect the stop mode current consumption. 10.9 analog input the external analog voltage value to be converted by the a/d converter is sampled on an internal capacitor through a resistive path provided by input-selection switches and a sampling aperture time switch. sampling time is limited to 12 bus clock cycles. after sampling, the analog value is stored on a capacitor and held until the end of conversion. during this hold time, the analog input is disconnected from the internal a/d system and the external voltage source sees a high impedance input. the equivalent analog input during sampling is a rc low-pass filter with resistance around 50 k ? and a capacitance of around 8pf. (it should be noted that these are typical values measured at room temperature). freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 analog to digital converter nondisclosure agreement required figure 10-4 electrical model of an a/d input pin be sure that pins used as analog inputs are configured as inputs with their appropriate pull-up resistors disabled (enabled after reset). 10.10 conversion accuracy definitions this section explains the terminology used to specify the analog characteristics of the a/d converter. 10.10.1 transfer curve the ideal transfer curve can be thought of as a staircase of uniform step size with perfect positioning of the endpoints. figure 10-5 shows the ideal transfer curve of an 8-bit a/d converter. * * this analog switch is closed only during the 12-cycle sample time input protection diffusion pa1... pa6 dac capacitance ~ 50 k ? 8pf < 10pf vrefl / vss vdd vss freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
analog to digital converter conversion accuracy definitions mc68hc(8)05pv8/a ? rev. 1.9 technical data analog to digital converter nondisclosure agreement required figure 10-5 transfer curve of an ideal 8-bit a/d converter 10.10.2 monotonicity the characteristic of the transfer function whereby increasing the input signal results in the output never decreasing. 10.10.3 quantization error also known as digitization error or uncertainty. it is the inherent error involved in digitizing an analog signal due to the finite number of steps at the digital output versus the infinite number of values at the analog input. input voltage (lsb) conversion result $00 $01 $02 $03 $fd $fe $ff 1 2 3 254 255 1lsb = vrefh / 255 1-bit accuracy 253 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 analog to digital converter nondisclosure agreement required 10.10.4 offset error the offset error is the dc shift of the entire transfer curve of an ideal converter. 10.10.5 gain scale error the gain error is an error in the input to output transfer ratio. gain error causes an error in the slope of the transfer curve. 10.10.6 differential linearity error the differential linearity error is the difference between actual analog voltage change and the ideal (1lsb) voltage change at any code change. 10.10.7 integral linearity error the integral linearity error is the deviation from the best fitting line through all a/d code changes. 10.10.8 total unadjusted error the total unadjusted error is the maximum error that occurs without adjusting offset and gain errors. this error is a combination of offset, scale and integral linearity errors. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data pulse width modulator nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 11. pulse width modulator 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.4 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.1 pwm control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11.4.2 pwm data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.4.3 pwm period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6 pwm during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.7 pwm during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.8 frame frequency examples. . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.2 introduction the pulse width modulator (pwm) system has one channel. the pwm has a programmable period of pwmprxt = pwmpr / f pwm , where pwmpr is a programmable period (1... 256) and t = 1 / f pwm can be 1/f osc , 1.5/f osc , 2/f osc , 3/f osc and so on. f osc is the oscillator frequency. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 pulse width modulator nondisclosure agreement required figure 11-1 pwm block diagram 11.3 functional description the pwm is capable of generating signals from 0% to 100% duty cycle. a $00 in the pwm data register yields an off output (0%), but an $ff yields a duty of 255/256 (assuming the pwm period register is set to $ff). to achieve the 100% duty (on output), the polarity control bit is set while the data register contains $00. when not in use the pwm system can be shut off to save power by clearing the pwmon bit in the pwm control register. the pwm starts conversion immediately after setting pwmon. the pwm output can have an active high or an active low pulse under software control. pwm osc1 pol pwmon pra0 ? 3 hc05 data bus cycle loadable counter comparator buffer pwm control register pwm pin logic clock generator f pwm freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
pulse width modulator functional description mc68hc(8)05pv8/a ? rev. 1.9 technical data pulse width modulator nondisclosure agreement required figure 11-2 pwm waveforms (pol = 0, active low), pwmpr = $ff figure 11-3 pwm waveforms (pol = 1, active high), pwmpr = $cf a0 80 pwmdat = $00 (pwmpr + 1) / f pwm ff conversion n ? 1 complete conversion n complete pwmdat = $00 a0 conversion n ? 1 complete conversion n complete (pwmpr + 1) / f pwm pwmdat = $ff ( > pwmpr, -> output permanent low) pwmdat / f pwm (pwmpr - pwmdat) / f pwm freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 pulse width modulator nondisclosure agreement required 11.4 registers associated with the pwm system, there are a pwm data register, a pwm period register and a pwm control register. these registers can be written to and read at any time. writing to the data or the period register takes effect when the whole pwm system is started by switching on the pwmon bit or when a conversion cycle is complete. after reset the user should write to the prescaler bits prior to enabling the pwm system. this prevents an erroneous duty cycle from being driven. 11.4.1 pwm control register pwmon ? pwm module on 1 = pwm module operating 0 = pwm module stopped pol ? pwm polarity when set, this bit makes the active pwm pulse high. when cleared, the output is active low (e.g. $00 in the data register yields an all high signal for pola = 0). the programmed polarity bit is copied into a shadow polarity bit when the pwm data register is written. at the end of the current conversion, the shadow polarity bit takes effect. 1 = pwm polarity active high 0 = pwm polarity active low cycle ? pwm cycle completed this bit indicates the completion (reload of pwm data and period) of a pwm cycle. this flag is cleared by writing a 1 to the bit position. 1 = pwm registers were reloaded after last flag clear 0 = pwm registers were not reloaded after last flag clear $002d bit 7 654321bit 0 read: pwmon pol 0 cycle pra3 pra2 pra1 pra0 write: reset:00000000 figure 11-4 pwm control register (pwmcr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
pulse width modulator registers mc68hc(8)05pv8/a ? rev. 1.9 technical data pulse width modulator nondisclosure agreement required pra3, pra2, pra1, pra0 ? pwm clock rate bits these bits select the input clock rate f pwm . for exact values see table 11-1 . the pwm clock rate bits are not latched until the end of conversion. they affect the pwm output immediately. for proper operation these control bits must not be changed during conversion. 11.4.2 pwm data register the pwm system has an 8-bit data register that holds the duty cycle for the pwm output. this register can be changed at any time. when the pwmdat register is updated, the programmed value, as well as the pol bit, take effect in the following conversion cycle. note that if the contents of pwmdat are higher than the contents of pwmpr the output will be permanently switched to the passive state (i.e. the same result as pwmdat = $00). table 11-1 pwm clock rate pra3:pra0 f pwm pra3:pra0 f pwm 0000 f osc 1000 f osc /16 0001 f osc /1.5 1001 f osc /24 0010 f osc /2 1010 f osc /32 0011 f osc /3 1011 f osc /48 0100 f osc /4 1100 f osc /64 0101 f osc /6 1101 f osc /96 0110 f osc /8 1110 f osc /128 0111 f osc /12 1111 f osc /192 $002e bit 7 654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 figure 11-5 pwm data register (pwmdat) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 pulse width modulator nondisclosure agreement required 11.4.3 pwm period register the pwm system has an 8-bit period register that holds the pwm period. the frame frequency of the pwm system is defined as f frame =f pwm /(pwmpr + 1). this register can be written at any time. the period of the output changes after the current cycle. 11.5 pwm during wait mode the pwm continues normal operation during wait mode. to decrease power consumption during wait it is recommended to shut off the pwm by clearing the pwmon bit if the pwm system is not used. 11.6 pwm during stop mode in stop mode the oscillator is stopped, causing the pwm to cease functioning. any signal in process is aborted in whatever phase the signal happens to be in. 11.7 pwm during reset upon reset the pwmon and pra3 ? 0 bits in the pwm control register are cleared, the data register is written with $00 and the polarity bit is reset. this in effect disables the pwm system and sets the output driving high. the user should write to the data register, the period register, the polarity bit and the clock rate bits prior to enabling the pwm system (i.e. prior to setting pwmon). this prevents an erroneous duty cycle from being driven. $002c bit 7 654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 11-6 pwm period register (pwmpr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
pulse width modulator frame frequency examples mc68hc(8)05pv8/a ? rev. 1.9 technical data pulse width modulator nondisclosure agreement required 11.8 frame frequency examples table 11-2 frame frequency for f osc = 4.2mhz pra3 ? pra0 pwmpr = $10 pwmpr = $40 pwmpr= $c7 pwmpr = $ff 0000 247khz 64.5khz 21khz 16.4khz 0001 165khz 43khz 14khz 10.9khz 0010 123khz 32.3khz 10.5khz 8.2khz 0111 20.6khz 5.38khz 1.75khz 1.37khz table 11-3 frame frequency for f osc = 2mhz pra3 ? pra0 pwmpr = $10 pwmpr = $40 pwmpr= $c7 pwmpr = $ff 0000 118khz 30.8khz 10khz 7.81khz 0001 78.4khz 20.5khz 6.67khz 5.21khz 0010 58.8khz 15.4khz 5khz 3.91khz 0111 9.8khz 1.28khz 833hz 651hz freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 pulse width modulator nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data voltage regulator nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 12. voltage regulator 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.3 internal power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.4 5v regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 12.5 trimming the voltage regulator . . . . . . . . . . . . . . . . . . . . . . . 156 12.2 introduction the mc68hc(8)05pv8/a contains a low-power, low-drop cmos on-chip fixed voltage regulator to provide internal power to the mcu from an external dc source. the mc68hc05pv8a contains on top of that a selectable standby regulator to achieve lower standby current. 12.3 internal power supply the on-chip voltage regulation and power supply control circuitry is comprised of two elements: the regulator and the low voltage reset (lvr) circuitry on the mc68hc(8)05pv8. in addition to that, the voltage regulator on mc68hc05pv8a comprises a standby regulator and a standby low voltage reset block. 12.4 5v regulator the 5v regulator accepts an unregulated input supply and provides a regulated 5v supply to all the digital sections of the device. the output of this regulator is also connected to the vdd pin to allow for decoupling and to provide an external power source. the voltage regulator handles the generation of low voltage resets. for details refer to 5.12 low voltage reset . freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 voltage regulator nondisclosure agreement required any loss of v dd sufficient to trigger an lvr causes the device to be reset. the device remains in the reset state for the duration of the lvr condition or until the internal v dd drops below the functional level of the device, at which point reset no longer has meaning. if the drop in v dd that triggers an lvr is transient, then an internal rst is asserted for a minimum 4064 cycles of the cpu bus clock, ph2 (the por delay). on the mc68hc05pv8a, the low voltage reset is generated by a second low voltage reset generator with a lower threshold as long as the ulpm bit is set. for this reason, it is mendatory to have the ulpm bit cleared as long as the mcu is in normal operation. 12.5 trimming the voltage regulator the output of the voltage regulator can be trimmed to reach a higher accuracy. this is performed by setting the vt2, vt1 and vt0 bits in the mftest register table 12-1 illustrates the effect of the trimming bits to v dd in increase or decrease of the output voltage by trimming steps (typically 40mv). $002f bit 7 654321bit 0 read: hvtoff 00 vscal lsoff vt2 vt1 vt0 write: ?? reset:00000000 figure 12-1 mftest register (mftest) table 12-1 trimming effect vt2 vt1 vt0 effect 000 0 001 ? 1 010 ? 2 011 ? 3 100+4 101+3 110+2 111+1 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data eeprom nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 13. eeprom 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.3 eeprom control register (eepcr) . . . . . . . . . . . . . . . . . . . 158 13.4 eeprom options register (eeopr) . . . . . . . . . . . . . . . . . . 159 13.5 eeprom read, erase and programming procedures . . .160 13.5.1 read procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.2 erase procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.5.3 programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . 160 13.6 operation in stop and wait modes. . . . . . . . . . . . . . . . . . . 161 13.2 introduction the eeprom on this device is 128 bytes and is located from address $0180 to $01ff. the user programs the eeprom on a single-byte basis by manipulating the eeprom control register (eepcr). an erased byte reads as $ff and any programmed bit reads as 0. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 eeprom nondisclosure agreement required 13.3 eeprom control register (eepcr) eeosc ? eeprom rc oscillator control when this bit is set, the eeprom section uses the internal rc oscillator instead of the cpu clock. the user must wait a time t rcon after setting the eeosc bit to allow the rc oscillator to stabilize. eeosc is readable and writable. it should be set by the user when the internal bus frequency falls below 1.5 mhz. reset clears this bit. eer1, eer0 ? erase select bits eer1 and eer0 form a 2-bit field that is used to select one of three erase modes: byte, block, or bulk erase. table 13-1 shows the modes selected for each bit configuration. these bits are readable and writable and are cleared by reset. in byte erase mode, only the selected byte is erased. in block mode, a 128-byte block of eeprom is erased. the eeprom memory space is divided into two 64-byte blocks ($0180 ? $01bf, $01c0 ? $01ff) and performing a block erase on any address within a block will erase the entire block. in bulk erase mode, the entire 128 byte eeprom section is erased. a block protect function applies on block2 of the eeprom memory space. see 13.4 eeprom options register (eeopr) for more details. $000c bit 7 654321bit 0 read: 0 0 0 eeosc eer1 eer0 eelat eepgm write: reset:00000000 figure 13-1 eeprom control register (eepcr) table 13-1 erase mode select eer1 eer0 mode 0 0 no erase 0 1 byte erase 1 0 block erase (block1 or block2) 1 1 bulk erase (block1 & block2) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
eeprom eeprom options register (eeopr) mc68hc(8)05pv8/a ? rev. 1.9 technical data eeprom nondisclosure agreement required eelat ? eeprom programming latch the eelat bit is the eeprom programming latch enable. when eelat is at 0, the eer1, eer0 and eepgm bits are reset to zero. when the eelat bit is clear, data can be read from the eeprom. when set, this bit allows the address and data to be latched into the eeprom for further programming or erase operation. address and data can only be latched when the eepgm bit is at 0. stop, reset and power-on reset reset the eelat bit. eepgm ? eeprom programming power enable eepgm must be written to enable (or disable) the eepgm function. when set, eepgm turns on the charge pump and enables the programming (or erasing) power to the eeprom array. when clear, this power is switched off. this allows pulsing of the programming voltage to be controlled internally. this bit can be read at any time, but can only be written to if eelat = 1. if eelat is not set, then eepgm cannot be set. this bit is cleared by reset or when eelat = 0. 13.4 eeprom options register (eeopr) this register contains the secure and protect functions for the eeprom and allows the user to select options in a non-volatile manner. the contents of the eeopr register are loaded into data latches with each power-on or external reset. the register is implemented in eeprom, therefore reset has no effect on the individual bits. eeprt ? eeprom protect bit in order to achieve a higher degree of protection, the eeprom is split into two 64-byte blocks. block 1 ($0180 - $01bf) cannot be protected. block 2 ($01c0 - $01ff) is protected by the eeprt bit of the options $0180 bit 7 654321bit 0 read: eeprt write: reset: na na na na na na na na figure 13-2 eeprom options register (eeopr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 eeprom nondisclosure agreement required register. when this bit is set from 0 to 1 (erased) the protection remains until the next power-on or external reset. eeprt can only be written to 0 when the elat bit in the eeprom control register is set. 1 = block 2 of the eeprom array is not protected; all 128 bytes of eeprom can be accessed for any read, erase or programming operations 0 = block 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful 13.5 eeprom read, erase and programming procedures 13.5.1 read procedure to read data from eeprom the eelat bit must be clear. eepgm, eer1 and eer0 are forced to zero. the eeprom is read as if it were a normal rom. the charge pump generator is off since eepgm is zero. if a read is performed while elat is set, data will be read as $ff. 13.5.2 erase procedure there are three types of erase operation mode (see table 13-1 erase mode select ), byte erase, block erase or bulk erase. to erase a byte of eeprom set eelat = 1, er1 = 0 and er0 = 1, write to the address to be erased and set eepgm for a time t ebyte . to erase a block of eeprom set eelat = 1, er1 = 1 and er0 = 0, write to any address in the block and set eepgm for a time t ebloc . for a bulk erase set eelat = 1, er1 = 1, and er0 = 1, write to an address in the array with a0 or a1 = 1, and set eepgm for a time t ebulk . 13.5.3 programming procedure to program the content of eeprom, set eelat bits, write data to the desired address and set the eepgm bit. after the required programming delay t eepgm , eelat must be cleared. this also resets eepgm. during freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
eeprom operation in stop and wait modes mc68hc(8)05pv8/a ? rev. 1.9 technical data eeprom nondisclosure agreement required a programming operation, any access of eeprom will return $ff. to program a second byte, eelat must be cleared before it is set, otherwise the programming will have no effect. 13.6 operation in stop and wait modes the rc oscillator for the eeprom is automatically disabled when entering stop mode. the user may want to ensure that the rc oscillator is disabled before entering wait mode to help conserve power. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 eeprom nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data program eeprom nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 14. program eeprom 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 14.3 programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 14.4 eeprom protection mechanism . . . . . . . . . . . . . . . . . . . . . . 165 14.5 options register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 14.2 introduction the program eeprom on the MC68HC805PV8 is 7936 bytes and is located from address $2000 to $3eff. it also holds 16 bytes of user vectors ranging from $3ff0 to $3fff. programming circuitry embedded in the eeprom block allows a group of up to four different bytes to be written or erased simultaneously. these four bytes must be located in the set of addresses which differ only in the two least significant bits. an internal charge pump is provided, avoiding the necessity to supply a high voltage for erase and programming functions. in order to achieve a higher degree of security for stored data, there is no capability for bulk or row erase in single chip mode. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 program eeprom nondisclosure agreement required 14.3 programming register three bits of the program eeprom programming register have been provided in order to control the eeprom operations. rcon ? rc oscillator on this bit determines the state of the rc oscillator. this oscillator should be switched on when the device is operated below 1mhz bus clock. on higher bus speeds, this bit can be switched off to reduce power consumption 1 = rc oscillator switched on 0 = rc oscillator switched off bulk ? bulk erase enable this bit determines the selection of 4-byte or bulk erase mode. for programming the array, this bit must be cleared. 1 = bulk erase mode selected 0 = 4-byte erase mode selected erab ? write/erase mode selection the status of this bit is latched on the first store to eeprom following the clearing of the latb bit. 1 = eeprom write mode 0 = eeprom erase mode latb ? programming latch enable when cleared, this bit allows data and address to be latched into the corresponding eeprom flip-flops during the first store access to the same eeprom address. any subsequent eeprom store instruction modifies the data register defined by address bits 0 and 1. for normal access to the eeprom, this bit must be set in order to force the eeprom address latch to the transparent mode. this bit also $000d bit 7 654321bit 0 read: rcon bulk erab latb pgmb write: reset: ??? 10111 figure 14-1 program eeprom control register (peecr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
program eeprom eeprom protection mechanism mc68hc(8)05pv8/a ? rev. 1.9 technical data program eeprom nondisclosure agreement required controls the activation of the charge pump. the charge pump is not affected by wait mode, thus it is possible to wait the t era erase time or t prog programming time in wait mode. the eeprom is set to read mode when entering stop mode. 1 = eeprom read state 0 = activate charge pump; address and data may be latched for eeprom write. pgmb ? programming enable when cleared, this bit allows programming of the eeprom. it can only be cleared if the latb is already cleared and at least one eeprom write has occurred. this bit must be set when changing the address and data for programming new data. it is automatically set when latb is set. 1 = eeprom programming is inhibited 0 = eeprom programming is enabled 14.4 eeprom protection mechanism in order to achieve a higher degree of protection, inadvertent programming of the eeprom can be avoided by use of the eeprt bit of the options register. as long as this bit is not active (= 0), the whole array, except the first 4 bytes, can be erased or programmed. as soon as the eeprt bit is active (= 1), the eeprom is protected and becomes a read-only memory in single chip mode. note that programming cannot be done by software executed from this eeprom array! any attempt to erase or program a location in single-chip mode will then be unsuccessful. then the eeprom can be programmed only in bootloader mode. if the eeprt bit is then cleared (not protected), the eeprom will stay protected until the next power-on or external reset. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 program eeprom nondisclosure agreement required 14.5 options register the options register (optr), which also contains the protect function for the program eeprom in the MC68HC805PV8 version, is located at $2000 and allows the user to select options in a non-volatile manner. the contents of the optr register are loaded into data latches with each reset. eeprt ? program eeprom protect (only MC68HC805PV8) the eeprt bit allows the program eeprom ($2004 ? $3eff, $3ff0 ? $3fff) to be protected. if the eeprt bit is in the erased state (logic 0), the eeprom is not protected and can be used as a regular byte erasable eeprom. as soon as the eeprt bit is programmed to 1, the eeprom is hardware protected. the eeprom can still be read, but any attempt to erase or program will be unsuccessful. when this bit is cleared, protection remains until the next power-on or external reset occurs. in single chip mode, addresses $2000 ? $2003 are always write protected. 1 = eeprom protected 0 = eeprom erasable and writable copd ? cop (computer operating properly) reset disabled the copd bit allows the cop (computer operating properly timer) to be disabled. if the copd bit is in an erased state (logic 0), the cop is enabled. programming this bit (logic 1) disables the cop. changes to this bit do not take effect until the next power-on or external reset occurs. 1 = cop disabled 0 = cop enabled bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 optr r hvre htre stopr cme eeprt copd $2000 w reset na na na na na na na na figure 14-2 options register freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
program eeprom options register mc68hc(8)05pv8/a ? rev. 1.9 technical data program eeprom nondisclosure agreement required cme ? clock monitor enable the cme bit enables a watchdog for the oscillator circuit. when the frequency drops below a threshold (due to a brown-out or a defective element), when enabled, the clock monitor will reset the mcu and switch to an internal rc oscillator. 1 = clock monitor enabled 0 = clock monitor disabled stopr ? stop reset when enabled, the mcu will be reset when a stop instruction is to be executed. 1 = stop instruction causes reset 0 = stop instruction executes normally htre ? high temperature reset enable the htre bit allows the high temperature reset to be enabled. if the htre bit is in erased state (logic 0), the htr is disabled. programming this bit (logic 1) enables the htr. changes to this bit do not take effect until the next power-on or external reset occurs. see section 5. resets for details. 1 = htr enabled 0 = htr disabled hvre ? high voltage reset enable the hvre bit allows the high voltage reset to be enabled. if the hvre bit is in erased state (logic 0), the hvr is disabled. programming this bit (logic 1) enables the hvr. changes to this bit do not take effect until the next power-on or external reset occurs. see section 5. resets for details. 1 = hvr enabled 0 = hvr disabled freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 program eeprom nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data fast parallel interface nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 15. fast parallel interface 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.3.1 system control register . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.2 introduction the mc68hc(8)05pv8/a includes a fast parallel interface to access external peripheral components as fast as internal ones. the external address space ranges from $0030 to $003f and all 68hc05 instructions can be applied to this memory. since the data path is only 4-bits wide either the lines pa7 ? pa4 or the corresponding data bits in the port a data register are read depending on the state of the ddra7 ? ddra4 bits. 15.3 description if this interface is enabled by setting the fpie bit in the system control register pa0 ? 3 and pb0 ? 3 lines provide a 4 bit address, multiplexed with 4 bit wide data and timing control lines. the interface uses the lower port a lines (pa0 ? 3) to provide a 4 bit address multiplexed with 4 bit wide data. the timing is controlled by port b lines. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 fast parallel interface nondisclosure agreement required figure 15-1 basic fast peripheral interface timing the basic timing as shown in figure 15-1 is similar to the timing used on the hc11 parts in expanded multiplex mode. at the falling edge of the address strobe signal (as/pb0) the addresses on pa0 ? 3, the read/write signal (rw /pb1) and the chip select (cs /pb3) signal are valid. a high den/pb2 signal indicates that data are driven on the bus in cpu write cycles or that the peripheral ic can drive data in read cycles. whenever the fpiclk bit in the system control register is set the signals become only active when the range from $0030 ? $003f is addressed by the cpu thus significantly reducing electromagnetic noise. when using the a/d converter in conjunction with the fast peripheral interface the vrlen bit of port a configuration register must be cleared. see 7.4.4 port a configuration register . pb0 pa0-3 a0 ? 3d0 ? 3 rw cs pb1 pb2 pb3 as den freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
fast parallel interface description mc68hc(8)05pv8/a ? rev. 1.9 technical data fast parallel interface nondisclosure agreement required 15.3.1 system control register the following paragraphs describe the fpie and fpiclk bit function of the system control register. fpie ? fast peripheral interface enable if this bit is set the fast peripheral interface is enabled. pa0 ? 3 and pb0 ? 3 are no longer available as i/os. 1 = fast peripheral interface enabled 0 = fast peripheral interface disabled fpiclk ? fast peripheral clock if this bit is set, the fpi clocks are free running 1 = as and den only become active when cpu accesses $0030 ? $003f 0 = as and den always active $000a bit 7 654321bit 0 read: por intp intn inte wcop wcp fpie fpiclk write: reset:u0010000 figure 15-2 system control register (syscr) freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 fast parallel interface nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required technical data ? mc68hc(8)05pv8/a section 16. electrical specifications 16.1 contents 16.2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 16.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.4 program and data eeprom characteristics . . . . . . . . . . . . . 175 16.5 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 16.6 v dd referenced pins electrical characteristics . . . . . . . . . . . 178 16.7 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.8 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.9 power supply monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.9.1 v sup related reset and interrupts . . . . . . . . . . . . . . . . . . 183 16.10 down scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.11 die temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 16.12 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.13 a/d converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . 187 16.14 fast peripheral interface timing. . . . . . . . . . . . . . . . . . . . . . . 188 16.15 port c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 16.15.1 high voltage input/output (pc0 ? 4). . . . . . . . . . . . . . . . . . 189 16.15.2 contact sense circuitry to vbattery (pc0 ? 3) and to ground (pc1 ? 4 mc68hc(8)05pv8)/(pc1-3 mc68hc05pv8a) . .189 16.15.3 iso9141 driver (pc4) mc68hc(8)05pv8 . . . . . . . . . . . .190 16.15.5 low side driver (pc5/6, pvss) . . . . . . . . . . . . . . . . . . . . 191 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.2 maximum ratings (voltages referenced to v ss ) this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, it is recommended that lv in is constrained to the range v ss lv in v dd . reliability of operation could be affected if unused inputs are not connected to an appropriate logic voltage level (e.g., either v ss or v dd , or v ss for the high voltage pins). rating symbol value unit supply voltage v sup ? 0.3 to +40.0 v supply voltage without using the voltage regulator (v sup = v dd ) v dd ? 0.3 to +7.0 v input voltage (pa0 ? 7, pb0 ? 4, osc1) lv in1 v ss ? 0.3 to v dd +0.3 v input voltage (irq, reset) lv in2 v ss ? 0.3 to 12 v input voltage (pc0 ? 3) hv in1 v ss ? 0.3 to v sup +0.3 v input voltage (pc4) hv in2 v ss ? 5 to v sup +0.3 v applied voltage (pc5/6) hv in3 40 v applied voltage (pvss) hv in4 v ss to v dd v current drain per pin (all i/o, except pc4 ? 6) i out1 25 ma current drain per pin (vsup, vdd, vss, pc4) i out2 110 ma current drain per pin (pc5/6, pvss) i out3 700 ma operating junction temperature range t j ? 40 to +125 c storage temperature range t stg ? 65 to +150 c freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications thermal characteristics mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.3 thermal characteristics 16.4 program and data eeprom characteristics (v dd = 5.0vdc 10%, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) notes: 1. not applicable for mc68hc05pv8 characteristic symbol value unit thermal resistance soic28 ja 60 c/w rating symbol min max unit comment write/erase cycles program eeprom @ 10ms write time, t j = +125 c 100 - cycles see note 1 write/erase cycles data eeprom @ 10ms write time, t j = +125 c 10000 - cycles data retention eeproms 10 - years program eeprom programming time per 4 bytes t peepgm 5 10 ms see note 1 program eeprom erase time per 4 bytes t pebyt 5 10 ms see note 1 program eeprom bulk erase time t pebulk 400 500 ms see note 1 data eeprom programming time per byte t eepgm 510ms data eeprom erase time per byte t ebyt 510ms data eeprom erase time per block t eblock 510ms data eeprom bulk erase time t ebulk 510ms rc oscillators stabilization time (program & data eeprom) t rcon 5-t cyc freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.5 supply current (6v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) notes: 1. typical values reflect average measurements at mid point of supply voltage range ( vsup = 12v, vdd = 5v ) and t j = 25 c (applies to all tables). 2. run (operating), wait i sup : measured using external square wave clock source to osc1 (f osc = 4.2 mhz), all inputs 0.2 vdc from rail; no dc load, all programmable outputs are static, c l = 20 pf on osc2. 3. wait, stop i sup : all ports configured as inputs, lv il = 0.2vdc, lv ih = v dd ? 0.2vdc, hv i = 0.2vdc. 4. i sup1/2/3 are affected by the osc2 capacitance. 5. stop i sup4 measured with osc1 = pa0 ? 7 = pb0 ? 4 = irq = v ss . reset open. 6. the down scaler is automatically enabled after any reset and can be disabled by setting characteristic symbol typ max unit comment full circuit in run mode timer, a/d, pwm, cop on i sup1 4.4 9 ma see note 2,4 full circuit in wait mode timer, a/d, pwm, cop on timer, a/d, pwm, cop off i sup2 i sup3 1.95 1.45 - - ma ma see notes 2, 3 & 4 full circuit in stop mode (pv8) port c, op amp, power supply monitor, temperature sensor disabled i sup4 485 650 a see note 5 full circuit in stop mode (pv8a) port c, op amp, power supply monitor, temperature sensor disabled i sup4a 510 750 a see note 5 down scaler biasing current i sup5 100 - a see note 6 low side driver biasing current i sup6 280 - a see notes 7, 8, 13 contact sense circuitry internal reference biasing current i sup7 600 - a see notes 9 & 10 contact sense circuitry to v bat biasing current per output i sup8b 60 - a contact sense circuitry to ground biasing current per output i sup8g 120 - a see note 14 iso9141 driver biasing current on state i sup9 280 - a see note 11 iso9141 driver biasing current off state i sup10 35 - a port c input biasing current i sup11 10 - a see note 12 ultra low power mode i sup12 35 100 a see note 15, 16, 17 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications supply current mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required the vscal bit in the mftest register. 7. low side drivers and die temperature monitor can be disabled by setting lsoff bit in the mftest register. 8. the die temperature monitor is only disabled when the lsoff bit is set and the port c4 ddr bit is cleared as well. 9. there are two common reference blocks for pc0-4, one for contacts to vbat and one for contacts to ground. 10. this current is proportional to v sup . 11. the iso9141 driver can be disabled by clearing the pcddr4 bit. 12. the port c inputs can be disabled by setting the hvtoff bit in the mftest register. 13. low side drivers must be switched off. 14. comparators are automatically enabled with the corresponding output. 15. ultra low power mode is only available on mc68hc05pv8a. all i/o pins must be pulled to levels near vss or vdd/vsup resp.. 16. 6v < vsup < 12v. 17. in ultra low power mode, no external load on vdd, port a or port b is allowed. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.6 v dd referenced pins electrical characteristics (v dd = 5.0vdc 10%, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit comment output low voltage port a, port b v ol 1 v ol 2 ? ? ? ? 0.1 0.4 v v i load = 10 a i load = 1.6ma output low voltage reset v ol 3 ?? 1vi load = 1.6ma output high voltage port a, port b v oh 1 v oh 2 v dd ? 0.1 v dd ? 0.8 ? ? ? ? v v i load = ? 10 a i load = ? 0.8ma input high voltage port a, port b, irq , reset , osc1 v ih 0.7xv dd ? v dd v input low voltage port a, port b, irq , reset ,osc1 v il v ss ? 0.3xv dd v schmitt trigger hysteresis port a, port b, irq , reset v hys ? 1-v input pull-up current pa0 ? 3 i in 1 ? 80 250 a v in = v ss , see notes input pull-up current pa4 ? 7 i in 2 ? 0.8 2.5 ma input pull-up current pa0 ? 3 i in 3 ? 50 250 a v in = 0.7xv dd , see notes input pull-up current pa4 ? 7 i in 4 ? 0.5 2.5 ma internal pull-up resistor reset r rstpu 51950k ? input current irq , osc1 i in 6 ?? 1 av ss v in v dd i/o ports hi-z leakage current port a, port b i leak ? 1 ? 1 a pin capacitance port a, port b, reset , irq c pin ?? 10 pf not tested oscillator transconductance (i osc2 /v osc2 ) g m 0.9 ?? ma/v injection current pa1 ? 5 i inj -5 ? 5ma not production tested. see note 3. injection current pa0, pa6, pa7 i inj -2 ? 2ma injection current pb2 ? 4 i inj -1 ? 1ma freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications v dd referenced pins electrical characteristics mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required notes: (see next page) 1. the pull-up structures on port a0 ? 7 can be disabled by software, they are automatically enabled by each reset. 2. the pull-up structures on port a consist of enabled pmos devices. for input voltages near v ss they act like a constant current source. 3. a simple protection can be built with a series resistor: r > v max /i inj . the sum of currents during multiple injection should be limited below the maximum values for a single pin: r > (v max /i inj ) (number of pins). positive injection current can raise the supply voltage (v dd ). care must be taken in the ap- plication to ensure votages do not exceed the maximum ratings. characterized on the hc805pv8 and hc05pv8. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.7 voltage regulator (6v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) notes: 1. the current sourcing capability includes the current for the mcu core, for the ports and also for any external load. 2. refer to the maximum power dissipation. 3. the low voltage reset thresholds and hysteresis are measured relative to v dd with vt2..vt0 cleared in the mftest register (por condition, trim 0 configuration). 4. as the voltage regulator and the low voltage reset are using the same internal voltage ref- erence, it is ensured that the low voltage reset will only occur when the voltage regulator is out of regulation. 5. the stability is ensured with a decoupling capacitor between vdd and vss: c out 10 f with esr 10 ? . capacitor value and type should be choosen under consideration of the allowable vdd ripple in the particular application. characteristic symbol min typ max unit comment output voltage (6v v sup 16v) v dd 4.75 5.0 5.25 v i out 20ma output voltage (9v v sup 16v) in ultra low power mode v dd 3.7 v only on mc68hc05pv8a output voltage (5.5v < v sup 40v) v dd 4.5 5.0 5.5 v i out 30ma total output current i out ?? 30 ma see notes 1 & 2 line regulation (6v v sup 16v) v l i r ? 10 35 mv i out = 1ma load regulation v l o r ? 50 100 mv 1ma i out 20ma output voltage trimming step v s tep t rim - 40 - mv see chapter 12 low voltage reset low threshold v lvron 4.15 4.40 4.65 v see notes 3, 4 & figure 16-1 low voltage reset hysteresis v lvrh 40 100 200 mv low voltage reset low threshold in ultra low power mode v ulvron 2.6 v only on mc68hc05pv8a freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications voltage regulator mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required figure 16-1 low voltage reset waveform v dd reset v lvron v lvron + v lvrh freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.8 operational amplifier (device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit comment input offset voltage v io ? 120mv input common mode voltage range v icr v ss ? v dd ? 1.2 v large signal gain a vol ? 30 ? v/mv output voltage swing v oh v ss .. v dd ? 0.2 vr load = 50k ? to vss output short circuit current to v ss i scg ? 5 ? ma v id = 1v, v o = v ss , t j = 25 c output short circuit current to v dd i scp ? 50 ? a v id = ? 1v, v o = v dd , t j = 25 c slew rate sr ? 1 ? v/ s v in = 0.5v to 4.5v, r load = 50k ? to vss, c load = 25pf gain bandwidth product gbw ? 1 ? mhz f = 10khz freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications power supply monitor mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.9 power supply monitor 16.9.1 v sup related reset and interrupts (device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) note: see chapter 16.7 for the low voltage reset function. figure 16-2 vsup related reset and interrupts waveforms characteristic symbol min typ max unit comment high voltage reset on v hvron 34.5 36 37.5 v s ee figure 16-2 high voltage reset hysteresis v hvrh -1.5- v high voltage interrupt on v hvion 29 30.5 32 v high voltage interrupt hysteresis v hvih -1.5- v low voltage interrupt on v lvion 6.5 7.5 8.5 v low voltage interrupt hysteresis v lvih -0.6- v v sup v hvron ? v hvrh v hvron v hvion ? v hvih v hvion v lvion v lvion + v lvih high voltage reset high voltage interrupt low voltage interrupt freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.10 down scaler (device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) note: 1. the down scaler output is internally clamped at 5.3v typical. 2. the down scaler can only be observed by the a/d. the errors of the a/d has to be taken into account. 16.11 die temperature monitor (device untrimmed, v ss = 0vdc, unless otherwise noted) note: 1. by design the high temperature reset threshold is guaranteed to be (typically 25 c) above the high temperature interrupt threshold. 2. functionality of the device is not guaranteed for t j 125 c. see absolute maximum rat- ings. 3. measured on final test with vdd forced to 5.0v and atd switched to internal reference. p tot ~ 100mw. characteristic symbol min typ max unit comment voltage ratio = v sup /v ad7 4.85 5.1 5.35 ? 6v v sup 25.5v, see note 1,2 and chapter 10 characteristic symbol min typ max unit comment high temperature reset on t htron ? 150 ? c see note 1 & 2 high temperature reset hysteresis t htrh ? 7 ? c high temperature interrupt on t htion ? 125 ? c high temperature interrupt hystere- sis t htih ? 7 ? c temperature sensor a/d reading n tsout ? 142 ? -t j = 25 c temperature sensor a/d reading n tsout 171 202 - t a = 125 c, note 3 temperature sensor output sensitivity (a/d reading) s ? 0.45 ? 1/ c ? 40 c t j +125 c freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications control timing mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.12 control timing (v dd = 5.0vdc 10%, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) notes: 1. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . 2. the 2-bit timer prescaler is the limiting factor in determining timer resolution. 3. the minimum period t tltl should not be less than the number of cycles it takes to execute the capture interrupt service routine plus 24 t cyc . characteristic symbol min max unit frequency of operation crystal oscillator option (i.e. using the oscillator with a crystal) external clock source oscillator frequency with enabled clock monitor f osc f osc f osc 0.1 dc 0.4 4.2 4.2 4.2 mhz mhz mhz cycle time (2/f osc )t cyc 476 ? ns frequency detected as clock monitor error f osc dc 10 khz clock monitor backup-oscillator frequency f osc 0.8 4.2 mhz crystal oscillator start-up time t oxon ? 100 ms stop recovery start-up time t ilch ? 100 ms reset pulse width low t rl 120 ? ns interrupt pulse width low (edge-triggered) t ilih 120 ? ns interrupt pulse period t ilil note 1 ? t cyc osc1 pulse width t osc1 90 ? ns supply rise slew rate for por detection s rise 0.1 ? v/ s 16 bit timer resolution (note 2) input capture pulse width input capture period t resl t th , t tl t tltl 4.0 85 note 3 ? ? ? t cyc ns t cyc freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required figure 16-3 stop recovery timing diagram 3ffe 3ffe 3ffe 3ffe 3fff t rl t ilih osc1 1 reset irq 2 irq 3 internal clock internal address bus t ilch 4064 t cyc notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive selected. 3. irq pin level and edge-sensitive selected. 4.reset vector address shown for timing example. reset or interrupt vector fetch freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications a/d converter characteristics mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.13 a/d converter characteristics (v refh = v dd = 5.0vdc 10%, v refl = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted ) note: 1. t ad is either the bus clock period or the rc oscillator period (600ns typical). characteristic symbol min max unit comment resolution ? 8bit absolute accuracy ? 1.5 lsb including quantization error conversion range voltage reference high level voltage reference low level v refh v refl v refl v refl v ss v refh v dd v refh v v v a/d accuracy may decrease proportionately as v refh is reduced below v dd analog input voltage ? v refl v refh v must be within v ss and v dd zero input reading ? 00 01 hex v in = v refl full-scale reading ? fe ff hex v in = v refh conversion time (including sampling time) t c onv 32 t ad see note sampling time t s amp 12 t ad power-up time ?? 100 s a/d on current stabilization time t adon ? 100 s rc oscillator stabilization time t rcon ? 5 s a/d capacitance c ad ? 8 pf not tested freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.14 fast peripheral interface timing (v dd = 5.0vdc 10%, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) notes: 1. the first cycle denotes a read, the second a write cycle. 2. unlike in the hc11 as and den occur only when accessing the external memory if not enabled continuously. 3. osc1/osc2 input clock other than 50% duty cycle affect bus performance. 4. all timing is shown with respect to 20% v dd and 70% v dd , unless otherwise noted. figure 16-4 timing definition characteristic symbol min max unit comment den/as rise and fall time t r t f - - 25 25 ns ns see ? pulse width as, den high pw 210 - ns see ? address, cs , rw setup time t as 49 - ns see ? address, cs , rw hold time t ah 22 - ns see ? read data setup time t dsr 100 - ns see ? read data hold time t dhr 50 - ns see ? write data setup time t dsw 30 - ns see ? write data hold time t dhw 30 - ns see ? pb0/as pb1/rw a3:0 pa3:0 1 pb2/den 1 2 3 4 d3:0 r/w a3:0 1 1 5 6 r/w d3:0 7 8 pb3/cs freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications port c characteristics mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.15 port c characteristics 16.15.1 high voltage input/output (pc0 ? 4) (6v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) , 16.15.2 contact sense circuitry to vbattery (pc0 ? 3) and to ground (pc1 ? 4 mc68hc(8)05pv8)/(pc1-3 mc68hc05pv8a) (9v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit comment input low voltage hv il 0 ? 0.35 x v sup v input high voltage hv ih 0.65 x v sup ? v sup v input hysteresis voltage (pc0-3, pc4 on mc68hc(8)05pv8) v hys 0.1 0.1 x v sup ? v leakage current i l eak ? 10 ? 10 a inputs disabled input pull-down current i p ull d own ? 2.5 10 a inputs enabled, v in = v sup output low voltage (pc0 ? 3) v ol ? - 0.2 x v sup vi load = 1ma output high voltage (pc0 ? 4) (pc0-3 mc68hc05pv8a) v oh 0.8 x v sup - ? vi load = ? 1ma pin capacitance c out ?? 10 pf not tested debounce time (pc4 on mc68hc05pv8a) t db 1.5 s not tested characteristic symbol min typ max unit comment effective internal input resistance r in ?? 600 ? |i load | = 5ma total path resistance for low threshold r lt 2.5 4.0 ? k ? total path resistance for high threshold r ht ? 6.0 10.0 k ? total path resistance hysteresis r lt /r ht ? 0.75 ?? injection current i inj -5 ? 5ma not production tested. see also note 3 on page 179. freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required 16.15.3 iso9141 driver (pc4) mc68hc(8)05pv8 (6v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted notes: 1. the isomode bit in portc config0 register must be set. 2. calculated from 20% to 80% of the output swing. 3. pc4 is not short circuit protected to vsup. 16.15.4 iso9141 driver (pc4) mc68hc05pv8a (6v v sup 16v, device untrimmed, v ss = 0vdc, t j = ? 40 c to +125 c, unless otherwise noted characteristic symbol min typ max unit comment output falling edge slew rate sr f 357v/ s r pull-up = 510 ?, see note 2 output rising edge slew rate sr r 357v/ s rise fall slew rates symmetry ? sr ? 10 1v/ s output low voltage v ol ? 11.3v i load = 25ma leakage current (driver switched recessive) i leak -10 10 a-5v v in v sup current limitation threshold i lim 40 55 - ma see note 3 characteristic symbol min typ max unit comment output falling edge slew rate sr f -3.25 -2.25 -1.5 v/ s r pull-up = 510 ?, see note 2 output rising edge slew rate sr r 1.5 2.25 3.25 v/ s output low voltage v ol ? 11.4v i load = 25ma leakage current (driver switched recessive) i leak -10 10 a0v v in v sup input current (driver switched reces- sive) i leak -10 v in /5k ? 0.01 ma -16v v in 0v device powered current limitation threshold i lim 40 55 - ma see note 3 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
electrical specifications port c characteristics mc68hc(8)05pv8/a ? rev. 1.9 technical data electrical specifications nondisclosure agreement required 16.15.5 low side driver (pc5/6, pvss) (6v v sup 16v, device untrimmed, vss = 0 vdc, t j = ? 40 c to +125 c, unless otherwise noted) characteristic symbol min typ max unit comments output resistance r ds_on ? 24 ? i load = 100ma leakage current i l eak ? 10 ? 10 a 0v v in 16v positive output clamp voltage v c lamp 40 42.5 45 v over current threshold shutdown i s hut d own 300 500 700 ma freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 electrical specifications nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
mc68hc(8)05pv8/a ? rev. 1.9 technical data nondisclosure agreement required appendix b electrical specification for current communication interface b.1 current interface (pc5 or 6, pvss) (6v v sup 16v, device untrimmed , vss = 0 vdc, t j = -40 o c to +125 o c, unless otherwise noted) note : 1. with an external serial resistor 82.6 ? 1%(typically) between pvss and vss. characteristic symbol min typ max unit comments output current i lim2 30 35 40 ma see note 1 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
technical data technical data mc68hc(8)05pv8/a ? rev. 1.9 nondisclosure agreement required freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc...
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
mc68hc05pv8 / d rev 1.9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

▲Up To Search▲

Price & Availability of MC68HC805PV8

	To Download MC68HC805PV8 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .